Abstract: A method for fabricating a semiconductor device comprises: providing a substrate having a top surface; forming a bottom metal embedded in the substrate; forming a first etch stop layer, a first dielectric layer, a second etch stop layer and a second dielectric layer sequentially stacked on the top surface of the substrate; forming a semiconductor element disposed on the first etch stop layer, wherein the semiconductor element comprises a top plate and an etch stop pad disposed on the top plate; performing a first etching process to form a first partial via and a second partial via penetrating the second dielectric layer, the second etch stop layer and a portion of the first dielectric layer, wherein the first partial via is separated from the bottom metal by the first dielectric layer, and the second partial via is separated from the top plate by the etch stop pad.

Abstract: A method for fabricating a semiconductor device comprises: providing a substrate having a top surface; forming a bottom metal embedded in the substrate; forming a first etch stop layer, a first dielectric layer, a second etch stop layer and a second dielectric layer sequentially stacked on the top surface of the substrate; forming a semiconductor element disposed on the first etch stop layer, wherein the semiconductor element comprises a top plate and an etch stop pad disposed on the top plate; performing a first etching process to form a first partial via and a second partial via penetrating the second dielectric layer, the second etch stop layer and a portion of the first dielectric layer, wherein the first partial via is separated from the bottom metal by the first dielectric layer, and the second partial via is separated from the top plate by the etch stop pad.

Abstract: An apparatus for a user to conduct an accelerated soft error test (ASER) on a semiconductor sample is provided. The apparatus comprises a first component for holding the radiation source, where the radiation source may be either an alpha-particle or neutron-particle source. The apparatus comprises a second component for holding the semiconductor sample, where the semiconductor sample may be either a silicon wafer or semiconductor chip. The apparatus comprises a connecting assembly for placing the first component and the second component relative to each other at a plurality of positions that subject the semiconductor sample to a radiation stress from the radiation source at a plurality of stress efficiencies. Among the benefits provided are improved repeatability and credibility of ASER tests and reduced radiation exposures to operators of ASER tests.

Abstract: A battery-free remote controller includes an antenna, a plurality of key switches, and at least one electronic tag. The antenna is electrically connected to the plurality of key switches, and each electronic tag is electrically connected to the antenna through at least one of the key switches. Each electronic tag is corresponding to a device classification code, and each key switch is corresponding to an operation code. When one of the key switches is turned on, the electronic tag connected to the key switch is electrically connected to the antenna. At this time, the electronic tag uses a radio frequency signal received by the antenna as a power supply to output a remote control code containing the device classification code corresponding to the electronic tag and the operation code corresponding to the key switch, and the antenna transmits the remote control code.

Abstract: An apparatus for a user to conduct an accelerated soft error test (ASER) on a semiconductor sample is provided. The apparatus comprises a first component for holding the radiation source, where the radiation source may be either an alpha-particle or neutron-particle source. The apparatus comprises a second component for holding the semiconductor sample, where the semiconductor sample may be either a silicon wafer or semiconductor chip. The apparatus comprises a connecting assembly for placing the first component and the second component relative to each other at a plurality of positions that subject the semiconductor sample to a radiation stress from the radiation source at a plurality of stress efficiencies. Among the benefits provided are improved repeatability and credibility of ASER tests and reduced radiation exposures to operators of ASER tests.

Abstract: The present invention provides a single-chip but multi-output graphic system which provides identical or different graphic images on two display screens. The graphic system comprises at least a multimedia database, a first input process router, a second input process router, a first graphic processing unit and a second graphic processing unit. The first input process router selects the backdrop graphics and the moving object graphics (which are both provided by the multimedia database), feeds them into the first graphic processing unit and then outputs the processed graphics onto either the first display unit or the second display unit. Similarly, the second graphic processing units processes the backdrop graphics and the moving object graphics selected by the second input process router and then outputs the process graphics onto either the first display unit or the second display unit.

Abstract: The present invention provides a single-chip but multi-output graphic system which provides identical or different graphic images on two display screens. The graphic system comprises at least a multimedia database, a first input process router, a second input process router, a first graphic processing unit and a second graphic processing unit. The first input process router selects the backdrop graphics and the moving object graphics (which are both provided by the multimedia database), feeds them into the first graphic processing unit and then outputs the processed graphics onto either the first display unit or the second display unit. Similarly, the second graphic processing units processes the backdrop graphics and the moving object graphics selected by the second input process router and then outputs the process graphics onto either the first display unit or the second display unit.

Abstract: The present invention discloses an USB/OTG-interface storage card, wherein the USB/OTG interface unit is planarized such that the volume thereof can be reduced obviously and the USB/OTG-interface storage card can be more lightweight, slim. Further, the planarized interface unit enables the USB/OTG-interface storage card to be inserted completely inside a slot of an electronic device, and therefore, the user will no more scruple the bumps induced by the conventional USB/OTG-interface storage device's projecting from the electronic device.

Abstract: A charge integration algorithmic analog-to-digital converter utilizes one operational amplifier to perform an algorithm analog-to-digital conversation. In a first operating cycle, the ratio of a third capacitor to a fourth capacitor is used as a gain to determine an output voltage and an output bit. The output voltage is held in a first and second capacitors. In the second operating cycle, the ratio of the first capacitor to the second capacitor is used to determine an output voltage and an output bit. The output voltage is held in the third and fourth capacitors. The first and second operating cycles are repeated for generating converted digital data.