Abstract: An integrated circuit is provided and includes first transistors of a first circuit arranged in a first cell row having a first number of fin structures and a second transistor of a second circuit. The second transistor is coupled in parallel with a first element in the first transistors between first and second terminals of the first circuit, and arranged in a second cell row having a second number, different from the first number, of fin structures. The first element and the second transistor share a first gate extending in a first direction to pass through the first and second cell rows in a layout view. The second transistor is a duplication of the first element.

Abstract: A method includes supplying slurry onto a polishing pad; holding a wafer against the polishing pad with a piezoelectric layer interposed vertically between a pressure unit and the wafer; exerting a force on the piezoelectric layer using the pressure unit to make the piezoelectric layer directly press the wafer; generating, using the piezoelectric layer, a first voltage corresponding to a first portion of the wafer and a second voltage corresponding to a second portion of the wafer; tuning the force exerted on the piezoelectric layer according to the first voltage and the second voltage; and polishing, using the polishing pad, the wafer.

Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.

Abstract: A semiconductor device includes several first cell row an several second cell rows. The first cell rows extend in a first direction. Each of the first cell rows has a first row height. A first row of the first cell rows is configured for a first cell to be arranged. The second cell rows extend in the first direction. Each of the second cell rows has a second row height that is different from the first row height. At least one row of the second cell rows includes a portion for at least one second cell to be arranged. The portion has a third row height that is different from the first row height and the second row height.

Abstract: A semiconductor device includes several first cell row an several second cell rows. The first cell rows extend in a first direction. Each of the first cell rows has a first row height. A first row of the first cell rows is configured for a first cell to be arranged. The second cell rows extend in the first direction. Each of the second cell rows has a second row height that is different from the first row height. At least one row of the second cell rows includes a portion for at least one second cell to be arranged. The portion has a third row height that is different from the first row height and the second row height.

Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.

Abstract: An artificial antigen presenting cell system comprising one or more gelated human dendritic cells and a controlled release system capable of releasing one or more cytokines. Also provided herein are methods for producing the gelated human dendritic cells and uses of the artificial antigen presenting cell system for activating immune cells.

Abstract: A method of expanding natural killer cells, comprising: providing a population of internally gelated cells, each of which includes a gelated interior and a fluid cell membrane that contains one or more membrane-bound proteins each or collectively are capable of stimulating expansion of natural killer (NK) cells; and culturing a population of cells containing NK cells, which are capable of responding to the one or more membrane-bound proteins, with the population of internally gelated cells under conditions that allow expansion of NK cells.

Abstract: A carrier system that includes a nanocarrier and a peptide non-covalently associated with the nanocarrier. The peptide contains an adaptor peptide sequence fused to the N-terminus of a target peptide, the adaptor peptide sequence being designed to facilitate the association to the nanocarrier. Also disclosed is a method for improving the immunogenicity of a peptide antigen by fusing it to an adaptor peptide sequence to form an immunizing peptide and contacting the immunizing peptide with a compatible nanocarrier. Further, a method is provided for treating a condition by immunization with a target peptide that has been fused to an adaptor peptide sequence and thereby associated with a nanocarrier. The method induces an immune response against the target peptide for treating cancer, viral infection, bacterial infection, parasitic infection, autoimmunity, or undesired immune responses to a biologies treatment.

Abstract: A method of generating an internally fixed lipid vesicle, comprising: providing a precursor lipid vesicle that contains an aqueous interior enclosed by a lipid membrane, wherein the lipid membrane of the precursor lipid vesicle is non-permeable to a crosslinker; permeabilizing the lipid membrane transiently to generate a permeable vesicle; contacting the permeable vesicle with an inactive activatable crosslinker, whereby the inactive activatable crosslinker enters the permeable vesicle; allowing the permeable vesicle to return to a non-permeable vesicle; removing any extravesicular crosslinker; and activating the inactive activatable crosslinker to allow crosslinking to occur inside the non-permeable vesicle, whereby an internally fixed lipid vesicle is generated.

Abstract: A display panel structure and a manufacturing method thereof are disclosed. The display panel structure comprises a first substrate, a second substrate, at least a liquid crystal display (LCD) array, a plurality of LCD units, a plurality of first sealants and at least a second sealant. The second substrate is disposed corresponding to the first substrate. The LCD array is disposed between the first substrate and the second substrate. The LCD units are disposed within the LCD array. The first sealants are disposed around the LCD units, respectively. The second sealant is disposed around the LCD array in annulus. Thereby, the problems of the substrate peeling and fragment occurring in the process of the dorsal plating forming a conducting layer can be improved, and besides, the internal strike effect of the liquid crystal can be restrained, so as to enhance the technical yield.

Abstract: The present invention provides a pixel structure including a substrate, a thin-film transistor disposed on the substrate, a first insulating layer covering the thin-film transistor and the substrate, a common electrode, a connecting electrode, a second insulating layer, and a pixel electrode. The thin-film transistor includes a drain electrode. The first insulating layer has a first opening exposing the drain electrode. The common electrode and the connecting electrode are disposed on the first insulating layer. The connecting electrode extends into the first opening to be electrically connected to the drain electrode. The connecting electrode is electrically insulated from the common electrode. The second insulating layer covers the first insulating layer, the common electrode, the connecting electrode, and has a second opening exposing the connecting electrode. The pixel electrode is disposed on the second insulating layer and electrically connected to the connecting electrode through the second opening.

Abstract: The present invention provides a pixel structure including a substrate, a thin-film transistor disposed on the substrate, a first insulating layer covering the thin-film transistor and the substrate, a common electrode, a connecting electrode, a second insulating layer, and a pixel electrode. The thin-film transistor includes a drain electrode. The first insulating layer has a first opening exposing the drain electrode. The common electrode and the connecting electrode are disposed on the first insulating layer. The connecting electrode extends into the first opening to be electrically connected to the drain electrode. The connecting electrode is electrically insulated from the common electrode. The second insulating layer covers the first insulating layer, the common electrode, the connecting electrode, and has a second opening exposing the connecting electrode. The pixel electrode is disposed on the second insulating layer and electrically connected to the connecting electrode through the second opening.

Abstract: A delay locked loop includes a delay circuit capable of generating an output clock and further capable of generating a GATE signal in response to an aliased condition. A phase detector is coupled to the delay circuit and is capable of comparing a phase difference between a reference clock and the output clock from the delay circuit and generating a pump up signal if the output clock is lagging the reference clock. The phase detector is capable of generating a pump down signal if the output clock is leading the reference clock. A charge pump is coupled to the phase detector and is capable of generating a control voltage for controlling the delay provided to the output clock and capable of pulling up the control voltage in response to the GATE signal.

Abstract: A delay locked loop includes a delay circuit capable of generating an output clock and further capable of generating a GATE signal in response to an aliased condition. A phase detector is coupled to the delay circuit and is capable of comparing a phase difference between a reference clock and the output clock from the delay circuit and generating a pump up signal if the output clock is lagging the reference clock. The phase detector is capable of generating a pump down signal if the output clock is leading the reference clock. A charge pump is coupled to the phase detector and is capable of generating a control voltage for controlling the delay provided to the output clock and capable of pulling up the control voltage in response to the GATE signal.

Abstract: Systems and methods are described for adaptive equalizers. A circuit adapted to transform an equalizer input signal at a receiver to approximate an output signal at a transmitter includes an equalizer, a phase matching loop coupled to the equalizer, and an amplitude locking loop coupled to the equalizer. The equalizer can include a number of coarse band segments to provide coarse adjustment, at least one of which includes a number of fine band segments to provide fine adjustment. The systems and methods provide advantages in that multiple cable lengths can be serviced by a single equalizer, variations in the low frequency gain and the location of the zero point due to variations in manufacture and operating temperature are obviated, and a suitable gain can be provided at much higher frequencies.

Abstract: Systems and methods are described for implementing a backplane in the context of a stack of networking hubs based on a backplane connecter and for carrying out a method of configuring and terminating the backplane. A backplane connector includes a first voltage source; a plurality of connector contacts; a plurality of termination resistors, a first end of the plurality of termination resistors being coupled to the plurality of connector contacts; a first switch located between the first voltage source and a second end of the plurality of termination resistors; a first logic circuit coupled to the first switch, the first logic circuit closing the first switch when a layer composed by the backplane connector is both i) active and ii) either a top layer in a stack composed by the layer or a bottom layer in the stack.