Patents by Inventor Jung-Chi (Eric) LU

Jung-Chi (Eric) LU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Indium gallium zinc oxide layers for thin film transistors
    Patent number: 9502242
    Abstract: Embodiments of the present disclosure generally provide a method and apparatus for forming an IGZO active layer within a thin film transistor (TFT) device. In one embodiment, a method is provided for forming an IGZO active layer on a dielectric surface using a PECVD deposition process. In one embodiment, a method is provided for pretreating and passivating the dielectric surface for receiving the PECVD formed IGZO layer. In another embodiment, a method is provided for treating a PECVD formed IGZO layer after depositing said layer. In another embodiment, a method is provided for forming a multi-layer or complex layering structure of IGZO, within a PECVD processing chamber, for optimizing TFT electrical characteristics such as carrier density, contact resistance, and gate dielectric interfacial properties. In yet another embodiment, a method is provided for forming integrated layers for a TFT including IGZO within an in-situ environment of a cluster tool.
    Type: Grant
    Filed: January 19, 2015
    Date of Patent: November 22, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Tae Kyung Won, John M. White, Soo Young Choi, Jung-Chi (Eric) Lu
  • INDIUM GALLIUM ZINC OXIDE LAYERS FOR THIN FILM TRANSISTORS
    Publication number: 20150221507
    Abstract: Embodiments of the present disclosure generally provide a method and apparatus for forming an IGZO active layer within a thin film transistor (TFT) device. In one embodiment, a method is provided for forming an IGZO active layer on a dielectric surface using a PECVD deposition process. In one embodiment, a method is provided for pretreating and passivating the dielectric surface for receiving the PECVD formed IGZO layer. In another embodiment, a method is provided for treating a PECVD formed IGZO layer after depositing said layer. In another embodiment, a method is provided for forming a multi-layer or complex layering structure of IGZO, within a PECVD processing chamber, for optimizing TFT electrical characteristics such as carrier density, contact resistance, and gate dielectric interfacial properties. In yet another embodiment, a method is provided for forming integrated layers for a TFT including IGZO within an in-situ environment of a cluster tool.
    Type: Application
    Filed: January 19, 2015
    Publication date: August 6, 2015
    Inventors: Tae Kyung WON, John M. WHITE, Soo Young CHOI, Jung-Chi (Eric) LU