Abstract: An integrated circuit (IC) is provided. The IC includes a chip/die and a package. The chip/die includes a first bonding pad, a second bonding pad, a core circuit and a resistance unit. The first bonding pad is coupled to a signal path of the core circuit. The two ends of the resistance unit are respectively coupled to the first bonding pad and the second bonding pad. The package includes a pin and a low-pass circuit. The pin is electrically connected to the first bonding pad. The low-pass circuit is electrically connected to the second bonding pad.

Abstract: A current source and a method for designing the current source are provided. The current source is designed by a recursive rule and enables controllable delay lines to provide linear delay and occupy smaller area than conventional controllable delay lines with thermometer code current sources do.

Abstract: Provided is a measurement circuit for measuring a jitter of a clock signal. Delay elements delay the clock signal into delayed clock signal. Latches latch the delayed clock signals to indicate whether transition edges of the clock signal is within a window value which is corresponding to delays of the delay elements. Based on the latch result from the latches, a finite state machine generates control signals for controlling the delay elements. If the latch result indicates that the transition edges of the clock signal is not within the window value, the control signals adjust the delays of the delay elements and the window value. The jitter of the clock signal is measured based on the delays of the delay elements and the window value.

Abstract: A current source and a method for designing the current source are provided. The current source is designed by a recursive rule and enables controllable delay lines to provide linear delay and occupy smaller area than conventional controllable delay lines with thermometer code current sources do.

Abstract: Method and technique for analogue circuit synthesis. An analogue circuit usually includes many circuit components, and characteristics and functions of each circuit component are controlled by many corresponding parameters. In the presented invention, selected key design parameters of selected critical circuit components, as well as optimization targets, design specification or/and design constraint, are transformed into an optimization plan, and an optimization engine iterates circuit level or system level numerical simulations by changing values of the selected key design parameters recorded in the optimization plan, so as to find optimized parameters and circuit components which allow the analogue circuit to match the design specification/constraint and to approach the optimization target. Thus a systematic automation for analogue circuit synthesis/design/optimization is achieved.

Abstract: Provided is a measurement circuit for measuring a jitter of a clock signal. Delay elements delay the clock signal into delayed clock signal. Latches latch the delayed clock signals to indicate whether transition edges of the clock signal is within a window value which is corresponding to delays of the delay elements. Based on the latch result from the latches, a finite state machine generates control signals for controlling the delay elements. If the latch result indicates that the transition edges of the clock signal is not within the window value, the control signals adjust the delays of the delay elements and the window value. The jitter of the clock signal is measured based on the delays of the delay elements and the window value.

Abstract: A built-in memory current test circuit to test a memory on a chip is disclosed, comprising a built-in self-test circuit and a dynamic current generation module. The built-in self-test circuit is disposed on the chip to receive and process a test signal and generate a control signal to control operation of the memory and a current control code. The dynamic current generation module, also disposed on the chip, produces a test current into the memory based on the current control code. The current switch time is reduced in the built-in memory current test circuit, and an integrated test combining functional and stress tests can thus be performed.

Abstract: A calibration method of a mixed mode simulation calibrates standard delay times in a standard delay format and includes obtaining a digital output circuit from a digital circuit, obtaining an analog output circuit from an analog circuit, performing a simulation on the digital output circuit connected to the analog output circuit to obtain an ideal output, obtaining a first delay time according to the standard delay times of the digital output circuit, performing a calibrative analog-to-digital mixed mode simulation using the first delay time to obtain an analog-to-digital mixed output, comparing the ideal output and the analog-to-digital mixed output to calibrate the first delay time, and calibrating the standard delay times of the digital output circuit according to the calibrated first delay time.

Abstract: A built-in memory current test circuit to test a memory on a chip is disclosed, comprising a built-in self-test circuit and a dynamic current generation module. The built-in self-test circuit is disposed on the chip to receive and process a test signal and generate a control signal to control operation of the memory and a current control code. The dynamic current generation module, also disposed on the chip, produces a test current into the memory based on the current control code. The current switch time is reduced in the built-in memory current test circuit, and an integrated test combining functional and stress tests can thus be performed.

Abstract: IC with built-in self-test and design method thereof. The IC comprises an SD-ADC and a Dft circuit. The Dft circuit uses a digital stimulus signal to solve the deadlock problem of the on-chip analog testing and avoid thermal noise. Moreover, according to the design method of the IC, circuits having different specification can use the Dft circuit without performance degradation for original SD-ADC.

Abstract: IC with built-in self-test and design method thereof. The IC comprises an SD-ADC and a Dft circuit. The Dft circuit uses a digital stimulus signal to solve the deadlock problem of the on-chip analog testing and avoid thermal noise. Moreover, according to the design method of the IC, circuits having different specification can use the Dft circuit without performance degradation for original SD-ADC.