Patents by Inventor Jung-Chi HUANG
Jung-Chi HUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240072158Abstract: A method of forming a FinFET is disclosed. The method includes depositing a conductive material across each of a number of adjacent fins, depositing a sacrificial mask over the conductive material, patterning the conductive material with the sacrificial mask to form a plurality of conductive material segments, depositing a sacrificial layer over the sacrificial mask, and patterning the sacrificial layer, where a portion of the patterned sacrificial layer remains over the sacrificial mask, where a portion of the sacrificial mask is exposed, and where the exposed portion of the sacrificial mask extends across each of the adjacent fins. The method also includes removing the portion of the sacrificial layer over the sacrificial mask, after removing the portion of the sacrificial layer over the sacrificial mask, removing the sacrificial mask, epitaxially growing a plurality of source/drain regions from the semiconductor substrate, and electrically connecting the source/drain regions to other devices.Type: ApplicationFiled: August 30, 2022Publication date: February 29, 2024Inventors: Sung-Hsin Yang, Jung-Chi Jeng, Ru-Shang Hsiao, Kuo-Min Lin, Z.X. Fan, Chun-Jung Huang, Wen-Yu Kuo
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Publication number: 20210221327Abstract: A lock apparatus includes a bracket, an engagement module, and an actuation module. The engagement module is supported in the bracket and has an engagement member configured to move to a first position or a second position in a first axial direction along the first axial direction. The actuation module is connected to the bracket and includes a pushing member. The actuation module drives the pushing member to move to a first position or a second position in the second axial direction along the second axial direction. When the pushing member is at the first position in the second axial direction, the engagement member is at the first position in the first axial direction. When the pushing member is at the second position in the second axial direction, the engagement member is at the second position in the first axial direction.Type: ApplicationFiled: August 31, 2020Publication date: July 22, 2021Inventors: Jung-Chi Huang, Chia-Hao Chang, Yu-Min Chen
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Patent number: 10759382Abstract: A lock apparatus includes a bracket, an engagement module, and an actuation module. The engagement module is supported in the bracket and has an engagement member configured to move to a first position or a second position in a first axial direction along the first axial direction. The actuation module is connected to the bracket and includes a pushing member. The actuation module drives the pushing member to move to a first position or a second position in the second axial direction along the second axial direction. When the pushing member is at the first position in the second axial direction, the engagement member is at the first position in the first axial direction. When the pushing member is at the second position in the second axial direction, the engagement member is at the second position in the first axial direction.Type: GrantFiled: May 23, 2018Date of Patent: September 1, 2020Assignee: Gogoro Inc.Inventors: Jung-Chi Huang, Chia-Hao Chang, Yu-Min Chen
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Publication number: 20180345906Abstract: A lock apparatus includes a bracket, an engagement module, and an actuation module. The engagement module is supported in the bracket and has an engagement member configured to move to a first position or a second position in a first axial direction along the first axial direction. The actuation module is connected to the bracket and includes a pushing member. The actuation module drives the pushing member to move to a first position or a second position in the second axial direction along the second axial direction. When the pushing member is at the first position in the second axial direction, the engagement member is at the first position in the first axial direction. When the pushing member is at the second position in the second axial direction, the engagement member is at the second position in the first axial direction.Type: ApplicationFiled: May 23, 2018Publication date: December 6, 2018Inventors: Jung-Chi Huang, Chia-Hao Chang, Yu-Min Chen
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Patent number: 9367491Abstract: The present invention discloses a method of arbitrating among a plurality of channels to access a resource, comprising the steps of: providing each channel an address back-to-back counter; assigning each address back-to-back counter an initial value and a pre-defined threshold, wherein the address back-to-back counter is updated according to the activities of back-to-back access to the resource by the channel; and providing each channel a contiguous window setting to define a number of contiguous times for the channel to access the resource; wherein a channel being served is to be served for contiguous times defined by the contiguous window setting of the channel if the address back-to-back counter value of the channel is higher than the pre-defined threshold of the channel.Type: GrantFiled: December 31, 2013Date of Patent: June 14, 2016Assignees: Global Unichip, Corp., Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Chao Yu Chen, Min-Jung Fan-Chiang, Jung Chi Huang
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Publication number: 20150186053Abstract: The present invention discloses a method of arbitrating among a plurality of channels to access a resource, comprising the steps of: providing each channel an address back-to-back counter; assigning each address back-to-back counter an initial value and a pre-defined threshold, wherein the address back-to-back counter is updated according to the activities of back-to-back access to the resource by the channel; and providing each channel a contiguous window setting to define a number of contiguous times for the channel to access the resource; wherein a channel being served is to be served for contiguous times defined by the contiguous window setting of the channel if the address back-to-back counter value of the channel is higher than the pre-defined threshold of the channel.Type: ApplicationFiled: December 31, 2013Publication date: July 2, 2015Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., GLOBAL UNICHIP CORP.Inventors: Chao Yu Chen, Min-Jung Fan-Chiang, Jung Chi Huang
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Patent number: 9071477Abstract: A method and associated processing module for an interconnection system, providing a pre-tap tuning directing and a post-tap tuning directing. The interconnection system includes a transmitter filter and a receiver equalizer; the transmitter filter performs filtering according to a pre-tap and a post-tap, and the receiver equalizer performs equalization according to an equalizer tap. The pre-tap tuning directing includes: forming an indicative pattern with a plurality of data samples and a transition sample from an equalized signal, comparing if the indicative pattern matches predetermined pattern(s), and accordingly directing whether the pre-tap is incremented/decremented. The post-tap tuning directing selects whether the post-tap is incremented/decremented according to a positive/negative sign of the equalizer tap.Type: GrantFiled: October 9, 2013Date of Patent: June 30, 2015Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Juh Kang, Chen-Yang Pan, Jung-Chi Huang
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Publication number: 20150106673Abstract: The present invention discloses a memory channel bridge with a BIST module; and the memory channel bridge interfaces other channels in a SOC to access a memory module. During a DFT test, SOC memory channels and the BIST access the memory module concurrently by using an arbiter in the memory channel bridge to arbitrate the traffics from the SOC memory channels and the BIST to ensure the correctness and completeness of the whole design.Type: ApplicationFiled: October 16, 2013Publication date: April 16, 2015Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., GLOBAL UNICHIP CORP.Inventors: Jung Chi Huang, Wen Hsuan Hu, Chao Yu Chen
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Publication number: 20150098496Abstract: A method and associated processing module for an interconnection system, providing a pre-tap tuning directing and a post-tap tuning directing. The interconnection system includes a transmitter filter and a receiver equalizer; the transmitter filter performs filtering according to a pre-tap and a post-tap, and the receiver equalizer performs equalization according to an equalizer tap. The pre-tap tuning directing includes: forming an indicative pattern with a plurality of data samples and a transition sample from an equalized signal, comparing if the indicative pattern matches predetermined pattern(s), and accordingly directing whether the pre-tap is incremented/decremented. The post-tap tuning directing selects whether the post-tap is incremented/decremented according to a positive/negative sign of the equalizer tap.Type: ApplicationFiled: October 9, 2013Publication date: April 9, 2015Applicants: Taiwan Semiconductor Manufacturing Co., Ltd., Global Unichip CorporationInventors: Wen-Juh Kang, Chen-Yang Pan, Jung-Chi Huang
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Patent number: 8902960Abstract: Eye diagram scan circuit and associated method for a receiver circuit, including a level adjust circuit, a phase interpolator and a control module. The receiver circuit provides a first data signal and a primary phase data according to a received signal. The control module provides a phase offset data and a level offset data. The level adjust circuit adjusts a level of the received signal in respond to the level offset data; the phase interpolator triggers according to a sum of the phase offset data and the primary phase data, so a second data signal is provide in response to the level-adjusted received signal. The control module compares the first data signal and the second data signal, and accordingly provides an eye diagram scan result for the phase offset data and the level offset data.Type: GrantFiled: April 16, 2013Date of Patent: December 2, 2014Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Liang-Hung Chen, Yen-Chung Chen, Jung-Chi Huang
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Patent number: 8885695Abstract: A receiver circuit receives an incoming signal and accordingly provides an internal signal, and includes an equalizer, a slicer module and a counter module. The equalizer provides a signal level according to the incoming signal, the slicer module compares if the internal signal exceeds a level range; according to comparison result, the counter module provides a signal quality indication capable of indicating whether a bit error rate of signal receiving is greater than a predetermined reference bit error rate. One of an upper bound and a lower bound of the level range can equal the signal level, a distance between the upper bound and the lower bound is set according to a reference signal-to-noise ratio which associates with the reference bit error rate.Type: GrantFiled: June 26, 2013Date of Patent: November 11, 2014Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Juh Kang, Ming-Hsien Tsai, Jung-Chi Huang
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Patent number: 8572300Abstract: A physical coding sublayer includes a first channel configured to receive a first encoded data stream from a physical media attachment layer and to provide a first decoded data stream to a media access layer. The first channel includes a first circuit configured to detect synchronization headers in the first encoded data stream received from the physical media attachment layer, a decoding circuit configured to decode the encoded data stream and to adjust a width of the received data from a first width to a second width based on a signal identifying the synchronization headers received from the first circuit, and a first single configured to compensate for clock differences between the physical media attachment layer and the media access layer to which the first buffer provides the first decoded data stream.Type: GrantFiled: October 26, 2011Date of Patent: October 29, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Chi Wu, Meng-Chin Tsai, Liang-Hung Chen, Jung-Chi Huang
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Publication number: 20130272358Abstract: Eye diagram scan circuit and associated method for a receiver circuit, including a level adjust circuit, a phase interpolator and a control module. The receiver circuit provides a first data signal and a primary phase data according to a received signal. The control module provides a phase offset data and a level offset data. The level adjust circuit adjusts a level of the received signal in respond to the level offset data; the phase interpolator triggers according to a sum of the phase offset data and the primary phase data, so a second data signal is provide in response to the level-adjusted received signal. The control module compares the first data signal and the second data signal, and accordingly provides an eye diagram scan result for the phase offset data and the level offset data.Type: ApplicationFiled: April 16, 2013Publication date: October 17, 2013Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., GLOBAL UNICHIP CORPORATIONInventors: Liang-Hung Chen, Yen-Chung Chen, Jung-Chi Huang
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Publication number: 20130111083Abstract: A physical coding sublayer includes a first channel configured to receive a first encoded data stream from a physical media attachment layer and to provide a first decoded data stream to a media access layer. The first channel includes a first circuit configured to detect synchronization headers in the first encoded data stream received from the physical media attachment layer, a decoding circuit configured to decode the encoded data stream and to adjust a width of the received data from a first width to a second width based on a signal identifying the synchronization headers received from the first circuit, and a first single configured to compensate for clock differences between the physical media attachment layer and the media access layer to which the first buffer provides the first decoded data stream.Type: ApplicationFiled: October 26, 2011Publication date: May 2, 2013Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Chi WU, Meng-Chin TSAI, Liang-Hung CHEN, Jung-Chi HUANG