Patents by Inventor Jung-Chi Jeng

Jung-Chi Jeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10879186
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first mask layer over a dielectric layer. The first mask layer has a first trench, and the first trench has a first inner wall and a bottom surface. The method includes forming an anti-bombardment layer over a first top surface of the first mask layer. The method includes forming a second mask layer over the first inner wall of the first trench. The method includes removing the first portion, the first mask layer, the anti-bombardment layer, and the second mask layer to form a third trench in the dielectric layer. The method includes forming a conductive structure in the third trench.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Cherng Jeng, Shyh-Wei Cheng, Yun Chang, Chen-Chieh Chiang, Jung-Chi Jeng
  • Publication number: 20200402914
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first mask layer over a dielectric layer. The first mask layer has a first trench, and the first trench has a first inner wall and a bottom surface. The method includes forming an anti-bombardment layer over a first top surface of the first mask layer. The method includes forming a second mask layer over the first inner wall of the first trench. The method includes removing the first portion, the first mask layer, the anti-bombardment layer, and the second mask layer to form a third trench in the dielectric layer. The method includes forming a conductive structure in the third trench.
    Type: Application
    Filed: September 2, 2020
    Publication date: December 24, 2020
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Cherng JENG, Shyh-Wei CHENG, Yun CHANG, Chen-Chieh CHIANG, Jung-Chi JENG
  • Publication number: 20200295188
    Abstract: A method for forming a semiconductor device is provided. The method includes forming an isolation structure in a semiconductor substrate. The method includes forming a gate over the semiconductor substrate. The method includes forming a support film over the isolation structure. The support film is a continuous film which continuously covers the isolation structure and the gate over the isolation structure, the support film conformally covers a first portion of a top surface and a second portion of a first sidewall of the gate, the top surface faces away from the semiconductor substrate, the support film and a topmost surface of the active region do not overlap with each other, and the topmost surface faces the gate. The method includes after forming the support film, forming lightly doped regions in the semiconductor substrate and at two opposite sides of the gate.
    Type: Application
    Filed: June 4, 2020
    Publication date: September 17, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Chi JENG, I-Chih CHEN, Wen-Chang KUO, Ying-Hao CHEN, Ru-Shang HSIAO, Chih-Mu HUANG
  • Patent number: 10770401
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first mask layer over a dielectric layer. The method includes forming a second mask layer over a first top surface of the first mask layer, the inner wall, and the bottom surface. The method includes removing the second mask layer covering the bottom surface to form a second trench in the second mask layer. The method includes forming an anti-bombardment layer over a second top surface of the second mask layer. The second mask layer and the anti-bombardment layer are made of different materials. The method includes removing the first portion, the first mask layer, the second mask layer, and the anti-bombardment layer to form a third trench in the dielectric layer. The method includes forming a conductive structure in the third trench.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: September 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Cherng Jeng, Shyh-Wei Cheng, Yun Chang, Chen-Chieh Chiang, Jung-Chi Jeng
  • Patent number: 10680103
    Abstract: A method for forming a semiconductor device is provided. The method includes forming an isolation structure in a semiconductor substrate, and the isolation structure surrounds an active region of the semiconductor substrate. The method also includes forming a gate over the semiconductor substrate, and the gate is across the active region and extends onto the isolation structure. The gate has an intermediate portion over the active region and two end portions connected to the intermediate portion, the end portions are over the isolation structure. The method includes forming a support film over the isolation structure, and the support film is a continuous film which continuously covers the isolation structure and at least one end portion of the gate.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jung-Chi Jeng, I-Chih Chen, Wen-Chang Kuo, Ying-Hao Chen, Ru-Shang Hsiao, Chih-Mu Huang
  • Publication number: 20200118932
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first mask layer over a dielectric layer. The method includes forming a second mask layer over a first top surface of the first mask layer, the inner wall, and the bottom surface. The method includes removing the second mask layer covering the bottom surface to form a second trench in the second mask layer. The method includes forming an anti-bombardment layer over a second top surface of the second mask layer. The second mask layer and the anti-bombardment layer are made of different materials. The method includes removing the first portion, the first mask layer, the second mask layer, and the anti-bombardment layer to form a third trench in the dielectric layer. The method includes forming a conductive structure in the third trench.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Cherng JENG, Shyh-Wei CHENG, Yun CHANG, Chen-Chieh CHIANG, Jung-Chi JENG
  • Patent number: 10516048
    Abstract: A method of fabricating a semiconductor device includes following steps. A trench is formed in a substrate. A barrier layer and an epitaxy layer are formed in sequence in the trench. The barrier layer has a first dopant. A source/drain recess cavity is formed by etching at least the epitaxial layer. A source/drain region is formed in the source/drain recess cavity. The source/drain region has a second dopant.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Chih Chen, Ying-Lang Wang, Chih-Mu Huang, Ying-Hao Chen, Wen-Chang Kuo, Jung-Chi Jeng
  • Patent number: 10510671
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first mask layer over a dielectric layer. The first mask layer has a trench. The trench has an inner wall and a bottom surface. The method includes forming a second mask layer in the trench. The method includes removing the second mask layer covering the bottom surface to form a second trench in the second mask layer. The second trench exposes the bottom surface and is over a first portion of the dielectric layer. The remaining second mask layer covers the inner wall. The method includes removing the first portion, the first mask layer, and the second mask layer to form a third trench in the dielectric layer. The method includes forming a conductive structure in the third trench.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Cherng Jeng, Shyh-Wei Cheng, Yun Chang, Chen-Chieh Chiang, Jung-Chi Jeng
  • Publication number: 20190139895
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first mask layer over a dielectric layer. The first mask layer has a trench. The trench has an inner wall and a bottom surface. The method includes forming a second mask layer in the trench. The method includes removing the second mask layer covering the bottom surface to form a second trench in the second mask layer. The second trench exposes the bottom surface and is over a first portion of the dielectric layer. The remaining second mask layer covers the inner wall. The method includes removing the first portion, the first mask layer, and the second mask layer to form a third trench in the dielectric layer. The method includes forming a conductive structure in the third trench.
    Type: Application
    Filed: January 31, 2018
    Publication date: May 9, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Cherng JENG, Shyh-Wei CHENG, Yun CHANG, Chen-Chieh CHIANG, Jung-Chi JENG
  • Patent number: 10090392
    Abstract: A semiconductor device includes a metal oxide semiconductor device disposed over a substrate and an interconnect plug. The metal oxide semiconductor device includes a gate structure located on the substrate and a raised source/drain region disposed adjacent to the gate structure. The raised source/drain region includes a top surface above a surface of the substrate by a distance. The interconnect plug connects to the raised source/drain region. The interconnect plug includes a doped region contacting the top surface of the raised source/drain region, a metal silicide region located on the doped region, and a metal region located on the metal silicide region.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: October 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: I-Chih Chen, Chih-Mu Huang, Ling-Sung Wang, Ying-Hao Chen, Wen-Chang Kuo, Jung-Chi Jeng
  • Publication number: 20180061987
    Abstract: A method of fabricating a semiconductor device includes following steps. A trench is formed in a substrate. A barrier layer and an epitaxy layer are formed in sequence in the trench. The barrier layer has a first dopant. A source/drain recess cavity is formed by etching at least the epitaxial layer. A source/drain region is formed in the source/drain recess cavity. The source/drain region has a second dopant.
    Type: Application
    Filed: November 6, 2017
    Publication date: March 1, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: I-Chih CHEN, Ying-Lang WANG, Chih-Mu HUANG, Ying-Hao CHEN, Wen-Chang KUO, Jung-Chi JENG
  • Patent number: 9865731
    Abstract: A semiconductor device includes a p-type metal oxide semiconductor device (PMOS) and an n-type metal oxide semiconductor device (NMOS) disposed over a substrate. The PMOS has a first gate structure located on the substrate, a carbon doped n-type well disposed under the first gate structure, a first channel region disposed in the carbon doped n-type well, and activated first source/drain regions disposed on opposite sides of the first channel region. The NMOS has a second gate structure located on the substrate, a carbon doped p-type well disposed under the second gate structure, a second channel region disposed in the carbon doped p-type well, and activated second source/drain regions disposed on opposite sides of the second channel region.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: January 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: I-Chih Chen, Ying-Lang Wang, Chih-Mu Huang, Ying-Hao Chen, Wen-Chang Kuo, Jung-Chi Jeng
  • Publication number: 20170338342
    Abstract: A method for forming a semiconductor device is provided. The method includes forming an isolation structure in a semiconductor substrate, and the isolation structure surrounds an active region of the semiconductor substrate. The method also includes forming a gate over the semiconductor substrate, and the gate is across the active region and extends onto the isolation structure. The gate has an intermediate portion over the active region and two end portions connected to the intermediate portion, the end portions are over the isolation structure. The method includes forming a support film over the isolation structure, and the support film is a continuous film which continuously covers the isolation structure and at least one end portion of the gate.
    Type: Application
    Filed: August 7, 2017
    Publication date: November 23, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Chi JENG, I-Chih CHEN, Wen-Chang KUO, Ying-Hao CHEN, Ru-Shang HSIAO, Chih-Mu HUANG
  • Patent number: 9812569
    Abstract: A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate; a source/drain region having a first dopant in the substrate; a barrier layer having a second dopant formed around the source/drain region in the substrate. When a semiconductor device is scaled down, the doped profile in source/drain regions might affect the threshold voltage uniformity, the provided semiconductor device may improve the threshold voltage uniformity by the barrier layer to control the doped profile.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: November 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Chih Chen, Ying-Lang Wang, Chih-Mu Huang, Ying-Hao Chen, Wen-Chang Kuo, Jung-Chi Jeng
  • Patent number: 9728637
    Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and an isolation structure in the semiconductor substrate and surrounding an active region of the semiconductor substrate. The semiconductor device also includes a gate over the semiconductor substrate, and the gate has an intermediate portion over the active region and two end portions connected to the intermediate portion, and the end portions are over the isolation structure. The semiconductor device further includes a support film over the isolation structure and covering the isolation structure and at least one of the end portions of the gate. The support film exposes the active region and the intermediate portion of the gate.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: August 8, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Chi Jeng, I-Chih Chen, Wen-Chang Kuo, Ying-Hao Chen, Ru-Shang Hsiao, Chih-Mu Huang
  • Patent number: 9711468
    Abstract: A bonding pad structure comprises a first dielectric layer, a first conductive island in a second dielectric layer over the first dielectric layer and a via array having a plurality of vias in a third dielectric layer over the first conductive island. The structure also comprises a plurality of second conductive islands in a fourth dielectric layer over the via array. The second conductive islands are each separated from one another by a dielectric material of the fourth dielectric layer and in contact with at least one via of the via array. The structure further comprises a substrate over the second conductive islands. The substrate has an opening defined therein that exposes at least one second conductive island. The structure additionally comprises a bonding pad over the substrate. The bonding pad is in contact with the at least one second conductive island through the opening in the substrate.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: July 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Han Tsai, Jung-Chi Jeng, Yueh-Ching Chang, Volume Chien, Huang-Ta Huang, Chi-Cherng Jeng
  • Patent number: 9281215
    Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate. The semiconductor device also includes an isolation structure in the semiconductor substrate and surrounding an active region of the semiconductor substrate. The semiconductor device includes a gate over the semiconductor substrate. The gate has an intermediate portion over the active region and two end portions connected to the intermediate portion. Each of the end portions has a first gate length longer than a second gate length of the intermediate portion and is located over the isolation structure.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: March 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., LTD.
    Inventors: Jung-Chi Jeng, I-Chih Chen, Wen-Chang Kuo, Ying-Hao Chen, Ru-Shang Hsiao, Chih-Mu Huang
  • Publication number: 20150214165
    Abstract: A bonding pad structure comprises a first dielectric layer, a first conductive island in a second dielectric layer over the first dielectric layer and a via array having a plurality of vias in a third dielectric layer over the first conductive island. The structure also comprises a plurality of second conductive islands in a fourth dielectric layer over the via array. The second conductive islands are each separated from one another by a dielectric material of the fourth dielectric layer and in contact with at least one via of the via array. The structure further comprises a substrate over the second conductive islands. The substrate has an opening defined therein that exposes at least one second conductive island. The structure additionally comprises a bonding pad over the substrate. The bonding pad is in contact with the at least one second conductive island through the opening in the substrate.
    Type: Application
    Filed: April 10, 2015
    Publication date: July 30, 2015
    Inventors: Tsung-Han TSAI, Jung-Chi JENG, Yueh-Ching CHANG, Volume CHIEN, Huang-Ta HUANG, Chi-Cherng JENG
  • Publication number: 20150206945
    Abstract: A semiconductor device includes a metal oxide semiconductor device disposed over a substrate and an interconnect plug. The metal oxide semiconductor device includes a gate structure located on the substrate and a raised source/drain region disposed adjacent to the gate structure. The raised source/drain region includes a top surface above a surface of the substrate by a distance. The interconnect plug connects to the raised source/drain region. The interconnect plug includes a doped region contacting the top surface of the raised source/drain region, a metal silicide region located on the doped region, and a metal region located on the metal silicide region.
    Type: Application
    Filed: January 17, 2014
    Publication date: July 23, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: I-CHIH CHEN, CHIH-MU HUANG, LING-SUNG WANG, YING-HAO CHEN, WEN-CHANG KUO, JUNG-CHI JENG
  • Publication number: 20150200299
    Abstract: A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate; a source/drain region having a first dopant in the substrate; a barrier layer having a second dopant formed around the source/drain region in the substrate. When a semiconductor device is scaled down, the doped profile in source/drain regions might affect the threshold voltage uniformity, the provided semiconductor device may improve the threshold voltage uniformity by the barrier layer to control the doped profile.
    Type: Application
    Filed: March 25, 2014
    Publication date: July 16, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Chih CHEN, Ying-Lang Wang, Chih-Mu Huang, Ying-Hao Chen, Wen-Chang Kuo, Jung-Chi Jeng