Abstract: An embodiment is a semiconductor structure. The semiconductor structure includes a fin on a substrate. A gate structure is over the fin. A source/drain is in the fin proximate the gate structure. The source/drain includes a bottom layer, a supportive layer over the bottom layer, and a top layer over the supportive layer. The supportive layer has a different property than the bottom layer and the top layer, such as a different material, a different natural lattice constant, a different dopant concentration, and/or a different alloy percent content.

Abstract: A method of forming a FinFET is disclosed. The method includes depositing a conductive material across each of a number of adjacent fins, depositing a sacrificial mask over the conductive material, patterning the conductive material with the sacrificial mask to form a plurality of conductive material segments, depositing a sacrificial layer over the sacrificial mask, and patterning the sacrificial layer, where a portion of the patterned sacrificial layer remains over the sacrificial mask, where a portion of the sacrificial mask is exposed, and where the exposed portion of the sacrificial mask extends across each of the adjacent fins. The method also includes removing the portion of the sacrificial layer over the sacrificial mask, after removing the portion of the sacrificial layer over the sacrificial mask, removing the sacrificial mask, epitaxially growing a plurality of source/drain regions from the semiconductor substrate, and electrically connecting the source/drain regions to other devices.

Abstract: A first polymer layer is formed across a package region and a test region. A first metal pattern is formed in the package region and a first test pattern is simultaneously formed in the test region. The first metal pattern has an upper portion located on the first polymer layer and a lower portion penetrating through the first polymer layer, and the first test pattern is located on the first polymer layer and has a first opening exposing the first polymer layer. A second polymer layer is formed on the first metal pattern in the package region and a second test pattern is simultaneously formed on the first test pattern in the test region. The second polymer layer has a second opening exposing the upper portion of the first metal pattern, and the second test pattern has a third opening greater than the first opening of the first test pattern.

Abstract: A circuit device includes: a substrate having an insulative upper surface; a hydrophobic anti-plating layer of a hydrophobic material formed on the upper surface of the substrate and having at least one patterned through-hole for exposing a plating portion of the upper surface of the substrate; an active metal layer formed on the plating portion of the upper surface of the substrate and disposed in the patterned through-hole in the hydrophobic anti-plating layer; and an electroless deposited metal layer electroless deposited on the active metal layer.

Abstract: A collapsible computer table and frame includes two pairs of folding frames, a table board, an upper placing board and a lower placing board. Each folding frame consists of a horizontal frame rod for fixing a table board, a back frame rod with a lower end pivotally connected with an end of the horizontal frame rods, and a front feet and a rear feet pivotally connected with the horizontal frame rods. The back frame rod has its lower end pivotally connected with the horizontal frame rod and the rear feet. The folding connect rods are pivotally connected between the upper placing board to let the upper placing board to swing. The table board is fixed on the horizontal frame rods, folding connect rods are provided between the front and the rare foot, and then the whole computer table and frame can be easily collapsed.