Patents by Inventor Jung-Chin Chen
Jung-Chin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128853Abstract: A power converter that properly copes with the wiring defects on a feedback path is shown. According to a control signal, a power driver couples an input voltage to an energy storage element to provide an output voltage that is down-converted from the input voltage. The output voltage is further converted into a feedback voltage by a feedback circuit, and is entered to an error amplifier with a reference voltage for generation of an amplified error. A control signal generator generates the control signal of the power driver according to the amplified error. The power converter specifically has a comparator, which is enabled in a soft-start stage till the output voltage reaches a stable status. The comparator compares the amplified error with a critical value. When the amplified error exceeds the critical value, the input voltage is disconnected from the energy storage element.Type: ApplicationFiled: December 22, 2022Publication date: April 18, 2024Inventors: Jung-Sheng CHEN, Chih-Chun CHUANG, Yong-Chin LEE
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Publication number: 20240093364Abstract: A defect-reducing coating method is disclosed, which is characterized by making the coating surface of a sample face the bottom of the coating chamber, so that the sticking particles on side walls of the coating chamber will not fall on the coating surface of the sample during the coating process, thereby a smooth coating layer can be formed on the coating surface of the sample after the coating process is finished.Type: ApplicationFiled: November 21, 2022Publication date: March 21, 2024Applicant: MSSCORPS CO., LTD.Inventors: CHI-LUN LIU, JUNG-CHIN CHEN, BANG-HAO HUANG, YU-HAN CHEN, LIKO HSU
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Patent number: 11828800Abstract: The present invention discloses a method for preparing a semiconductor sample for failure analysis, which is characterized by using an adhesive layer comprising a non-volatile and non-liquid adhesive material with higher adhesion to the dielectric materials and lower adhesion to the metallic contact materials to selectively remove part of the dielectric materials in a large area with high uniformity, but completely remain the metallic contact materials, and not chemically react with the semiconductor specimens or even damage to the structures of interest to be analyzed, and different adhesive materials can be selected as the adhesive layer to control the adhesion to the dielectric layer, thereby the removed thickness of the dielectric layer can be controlled to provide a semiconductor specimen for failure analysis.Type: GrantFiled: August 23, 2021Date of Patent: November 28, 2023Assignee: MSSCORPS CO., LTD.Inventors: Chi-Lun Liu, Jung-Chin Chen, Shihhsin Chang
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Patent number: 11604153Abstract: A method of preparing a sample for physical analysis is disclosed, which is characterized by forming a low-temperature atomic layer deposition (ALD) metal nitride film or a low-temperature atomic layer deposition (ALD) metal oxynitride film by plasma-less enhanced atomic layer deposition (PLALD) at a temperature below 40° C. on a specimen to generate a sample for physical analysis to prevent the surface of sample for physical analysis from being damaged during physical analysis.Type: GrantFiled: October 15, 2020Date of Patent: March 14, 2023Assignee: MSSGORPS CO., LTD.Inventors: Chi-Lun Liu, Jung-Chin Chen, Bang-Hao Huang, Yu-Han Chen
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Patent number: 11468556Abstract: This inventions provides an artificial intelligence (A.I.) identified measuring method for a semiconductor image, comprising the steps of: providing an original image of a semiconductor; identifying a type and/or a category of the original image by an artificial intelligence; introducing a predetermined dimension measuring mode corresponding to the identified type and/or the identified category to scan the original image to generate a measurement signal of the original image; and extracting a designated object from the original image to generate a specific physical parameter of the original image after operation based on a measurement signal of the designated object and the measurement signal of the original image.Type: GrantFiled: February 25, 2021Date of Patent: October 11, 2022Assignee: MSSCORPS CO., LTD.Inventors: Chi-Lun Liu, Jung-Chin Chen, Bang-Hao Huang, Chao-Wei Chen
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Publication number: 20220155367Abstract: The present invention discloses a method for preparing a semiconductor sample for failure analysis, which is characterized by using an adhesive layer comprising a non-volatile and non-liquid adhesive material with higher adhesion to the dielectric materials and lower adhesion to the metallic contact materials to selectively remove part of the dielectric materials in a large area with high uniformity, but completely remain the metallic contact materials, and not chemically react with the semiconductor specimens or even damage to the structures of interest to be analyzed, and different adhesive materials can be selected as the adhesive layer to control the adhesion to the dielectric layer, thereby the removed thickness of the dielectric layer can be controlled to provide a semiconductor specimen for failure analysis.Type: ApplicationFiled: August 23, 2021Publication date: May 19, 2022Applicant: MSSCORPS CO., LTD.Inventors: CHI-LUN LIU, JUNG-CHIN CHEN, SHIHHSIN CHANG
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Publication number: 20210374927Abstract: This inventions provides an artificial intelligence (A.I.) identified measuring method for a semiconductor image, comprising the steps of: providing an original image of a semiconductor; identifying a type and/or a category of the original image by an artificial intelligence; introducing a predetermined dimension measuring mode corresponding to the identified type and/or the identified category to scan the original image to generate a measurement signal of the original image; and extracting a designated object from the original image to generate a specific physical parameter of the original image after operation based on a measurement signal of the designated object and the measurement signal of the original image.Type: ApplicationFiled: February 25, 2021Publication date: December 2, 2021Applicant: MSSCORPS CO., LTD.Inventors: CHI-LUN LIU, JUNG-CHIN CHEN, BANG-HAO HUANG, CHAO-WEI CHEN
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Publication number: 20210190707Abstract: This invention provides a method of preparing a sample for physical analysis, comprising the steps of providing a specimen, and forming a low-temperature atomic layer deposition film on the specimen to generate a sample for physical analysis.Type: ApplicationFiled: October 15, 2020Publication date: June 24, 2021Inventors: CHI-LUN LIU, JUNG-CHIN CHEN, BANG-HAO HUANG, YU-HAN CHEN
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Patent number: 7550336Abstract: A method for fabricating an NMOS transistor is disclosed. First, a substrate having a gate structure thereon is provided. A carbon implantation process is performed thereafter by implanting carbon atoms into the substrate for forming a silicon carbide region in the substrate. Subsequently, a source/drain region is formed surrounding the gate structure. By conducting a carbon implantation process into the substrate and a corresponding amorphorized implantation process before or after the carbon implantation process is completed, the present invention eliminates the need of forming a recess for accommodating an epitaxial layer composed of silicon carbide while facilitates the formation of silicon carbide from the combination of both implantation processes.Type: GrantFiled: November 21, 2006Date of Patent: June 23, 2009Assignee: United Microelectronics Corp.Inventors: Tsai-Fu Hsiao, Po-Yuan Chen, Jung-Chin Chen
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Publication number: 20070122987Abstract: A method for fabricating an NMOS transistor is disclosed. First, a substrate having a gate structure thereon is provided. A carbon implantation process is performed thereafter by implanting carbon atoms into the substrate for forming a silicon carbide region in the substrate. Subsequently, a source/drain region is formed surrounding the gate structure. By conducting a carbon implantation process into the substrate and a corresponding amorphorized implantation process before or after the carbon implantation process is completed, the present invention eliminates the need of forming a recess for accommodating an epitaxial layer composed of silicon carbide while facilitates the formation of silicon carbide from the combination of both implantation processes.Type: ApplicationFiled: November 21, 2006Publication date: May 31, 2007Inventors: Tsai-Fu Hsiao, Po-Yuan Chen, Jung-Chin Chen
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Patent number: 6905890Abstract: Under the first embodiment of the invention, back-end etching is applied to the specimen that needs to be inspected. Its surface is cleaned and mounted on a glass surface with the surface of the poly gate silicide that needs to be inspected being in contact with the surface of the glass. The exposed surface of the sample that is to be examined contains silicon, this silicon is removed. The gate oxide is then removed followed by the removal of the remaining poly of the gate structure. The second embodiment of the invention addresses poly gate inspection by enhanced (top surface of the gate electrode) gas etching of the gate electrode to remove gate oxide and silicon remains from the environment of the silicide. The specimen is etched back to the contact layer using a conventional Chemical Mechanical Polishing (CMP) process. The polished surface of the specimen is next exposed to XeF2, which selectively removes the oxide while the silicide remains in place.Type: GrantFiled: October 9, 2002Date of Patent: June 14, 2005Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jung-Chin Chen, Cheng-Han Lee
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Publication number: 20030032291Abstract: Under the first embodiment of the invention, back-end etching is applied to the specimen that needs to be inspected. Its surface is cleaned and mounted on a glass surface with the surface of the poly gate silicide that needs to be inspected being in contact with the surface of the glass. The exposed surface of the sample that is to be examined contains silicon, this silicon is removed. The gate oxide is then removed followed by the removal of the remaining poly of the gate structure. The second embodiment of the invention addresses poly gate inspection by enhanced (top surface of the gate electrode) gas etching of the gate electrode to remove gate oxide and silicon remains from the environment of the silicide. The specimen is etched back to the contact layer using a conventional Chemical Mechanical Polishing (CMP) process. The polished surface of the specimen is next exposed to XeF2, which selectively removes the oxide while the silicide remains in place.Type: ApplicationFiled: October 9, 2002Publication date: February 13, 2003Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Jung-Chin Chen, Cheng-Han Lee
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Patent number: 6482748Abstract: Under the first embodiment of the invention, back-end etching is applied to the specimen that needs to be inspected. Its surface is cleaned and mounted on a glass surface with the surface of the poly gate silicide that needs to be inspected being in contact with the surface of the glass. The exposed surface of the sample that is to be examined contains silicon, this silicon is removed. The gate oxide is then removed followed by the removal of the remaining poly of the gate structure. The second embodiment of the invention addresses poly gate inspection by enhanced (top surface of the gate electrode) gas etching of the gate electrode to remove gate oxide and silicon remains from the environment of the silicide. The specimen is etched back to the contact layer using a conventional Chemical Mechanical Polishing (CMP) process. The polished surface of the specimen is next exposed to XeF2, which selectively removes the oxide while the silicide remains in place.Type: GrantFiled: September 3, 1999Date of Patent: November 19, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jung-Chin Chen, Cheng-Han Lee