Abstract: A method of detecting hepatocellular carcinoma includes the steps of: detecting a methylation level of a CpG site of HOXA9 gene in a biological sample taken from a suspected subject; and comparing the methylation level to a reference methylation level of a CpG site of HOXA9 gene in another biological sample taken from a normal subject not suffering from hepatocellular carcinoma, wherein when the methylation level is higher than the reference methylation level, the suspected subject is likely to suffer from hepatocellular carcinoma, and wherein each of the biological samples is selected from the group consisting of a blood sample, a serum sample, and a plasma sample.

Abstract: A method of fabricating a non-volatile memory device is provided. A substrate including a first region and a second region is provided. Then, an uneven surface is formed on the substrate in the second region. Thereafter, a doped layer is formed in the substrate in the second region, and the doped layer is served as a control gate. Afterward, a dielectric layer is formed on the substrate in the first region and on the uneven surface of the substrate in the second region. Next, a floating gate is formed on the dielectric layer, and the floating gate is extended from the first region to the second region. Source and drain regions are formed in the substrate at opposite sides of the floating gate in the first region.

Abstract: A non-volatile memory device including a substrate, a dielectric layer, a floating gate, source and drain regions, a channel region, and a doped layer is provided. The substrate includes a first region and a second region, and the substrate has an uneven surface in the second region. The dielectric layer is located on the substrate in the first region and in the second region to cover the uneven surface. The floating gate is located on the dielectric layer in the first region and is continuously extended to the second region. The source and drain regions are located in the substrate at opposite sides of the floating gate in the first region. The channel region is located in the substrate between the source and drain regions. The doped layer is located on the uneven surface or in the substrate in the second region to serve as a control gate.

Abstract: A chip package comprises a semiconductor chip, a plurality of pins coupled to the semiconductor chip, and a conductive structure configured to form an electrical connection between the pins, wherein the electrical connection is configured to be disabled as the chip package is inserted into a socket. Since the pins are electrically connected by the conductive structure, the surge current caused by an ESD event can be distributed to all pins rather than to a single pin as the ESD event occurs. Consequently, all ESD protection circuits connected to the pins can be used to dissipate the surge current during the ESD event, and the circuit damage caused by the ESD can be dramatically reduced.

Abstract: In a method for copying data from an external storage device to a computer, the computer is provided with a basic input/output system (BIOS) program used for performing the method. The method includes the steps of: (a) after the computer is powered on, initializing the external storage device in response to a hot key trigger; and (b) storing the data from the external storage device to the computer. Since data is copied from the external storage device to the computer immediately after powering on the computer, efficiency is enhanced.

Abstract: A probing apparatus comprises a wafer chuck configured to receive a semiconductor wafer having a plurality of integrated circuit devices and test keys configured to monitor the fabrication quality of the integrated circuit devices, a carrier configured to receive a probe card having a plurality of probe needles configured to contact the test keys of the semiconductor wafer and collect electrical information of the integrated circuit devices, and an angular adjusting module configured to adjust the angle between the probe card and the semiconductor wafer by rotating the semiconductor wafer.

Abstract: A SEG combined with tilt implant method for forming semiconductor device is disclosed. The method includes providing a semiconductor structure which comprises an active area in between isolation regions in a substrate with the active area having a gate electrode formed thereon, wherein a spacer is formed on the sidewall of said gate electrode. Then, selective epitaxial growth regions are formed on the active area and the gate electrode. Next, the active area is implanted with an angle to form source/drain regions beside the bottom edge of the gate electrode. Then, the salicide process and backend processes are performed.

Abstract: A barbecue grill device includes two grill plates each are supported by a frame and the two grill plates are pivotally connected with each other so that the two grill plates are overlapped together. One of the grill plates has two flanges extending from two ends thereof and the other grill plate has two flanges extending from two ends thereof. When the second grill plate is overlapped on the first grill plate, the flanges on the first grill plate and the second grill plate are located side by side so as to reduce the total thickness of the overlapped grill plates.