Patents by Inventor Jung-Chun Wang

Jung-Chun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240243660
    Abstract: A switching converter having pulse skipping mode includes a power stage circuit, a feedback control circuit, an operating signal generator circuit and a pulse skipping circuit. The feedback control circuit generates an initial pulse width modulation (PWM) signal according the output power. The operating signal generator circuit masks a part of pulses of a clock signal according to a pulse width of a pulse skipping signal, so as to generate an adjusted PWM signal. The pulse skipping circuit adaptively generates a duty ratio signal according to an input voltage and an output voltage, so as to generate the pulse skipping reference signal related to a duty ratio of the initial PWM signal. The pulse skipping circuit compares an amplification signal with the pulse skipping reference signal to generate the pulse skipping signal. The power stage circuit converts the input power to the output power according to the adjusted PWM signal.
    Type: Application
    Filed: October 27, 2023
    Publication date: July 18, 2024
    Inventors: Jung-Sheng Chen, Chin-Chun Chuang, Che-Wei Chang, Shi-Xian Wang
  • Patent number: 5811853
    Abstract: A method of forming a memory cell structure in a semiconductor substrate that does not have a shorting problem between a floating gate and a source/drain region of the substrate by depositing a thick spacer oxide layer on top of the floating gate and the source/drain region to a sufficient thickness such that electrical insulation is provided thereinbetween to prevent the occurrence of a short or the formation of a silicide bridge. The invention is also directed to a semiconductor device fabricated by the method.
    Type: Grant
    Filed: August 13, 1996
    Date of Patent: September 22, 1998
    Assignee: Winbond Electronics Corp.
    Inventor: Jung-Chun Wang
  • Patent number: 5597751
    Abstract: A method of forming a memory cell structure in a semiconductor substrate that does not have a shorting problem between a floating gate and a source/drain region of the substrate by depositing a thick spacer oxide layer on top of the floating gate and the source/drain region to a sufficient thickness such that electrical insulation is provided thereinbetween to prevent the occurrence of a short or the formation of a silicide bridge. The invention is also directed to a semiconductor device fabricated by the method.
    Type: Grant
    Filed: December 20, 1995
    Date of Patent: January 28, 1997
    Assignee: Winbond Electronics Corp.
    Inventor: Jung-Chun Wang