Abstract: The invention provides an apparatus for demodulating an Address In Pre-groove (ADIP) symbol. The ADIP symbol is carried by a wobble signal of an optical disk and comprises a series of ADIP bits permuted according to one of a plurality of permutation patterns to make up the ADIP symbol. A wobble extraction module extracts the wobble signal from the optical disk. A reference wobble generator generates a reference wobble with the same frequency and phase as a fundamental frequency and phase of a positive wobble cycle of the wobble signal. A waveform difference measurement module then measures a difference between the wobble signal and the reference wobble to obtain a series of difference measurement values respectively corresponding to the ADIP bits. A pattern matching module then compares probabilities of the permutation of the ADIP bits agreeing with each of the permutation patterns according to the difference measurement values to determine the ADIP symbol.

Abstract: The invention provides an apparatus for demodulating an Address In Pre-groove (ADIP) symbol. The ADIP symbol is carried by a wobble signal of an optical disk and comprises a series of ADIP bits permuted according to one of a plurality of permutation patterns to make up the ADIP symbol. A wobble extraction module extracts the wobble signal from the optical disk. A reference wobble generator generates a reference wobble with the same frequency and phase as a fundamental frequency and phase of a positive wobble cycle of the wobble signal. A waveform difference measurement module then measures a difference between the wobble signal and the reference wobble to obtain a series of difference measurement values respectively corresponding to the ADIP bits. A pattern matching module then compares probabilities of the permutation of the ADIP bits agreeing with each of the permutation patterns according to the difference measurement values to determine the ADIP symbol.

Abstract: A DAC/ADC system for generating reference clocks for DAC/ADC by a look-up table method. The DAC/ADC system includes a sampling signal generator, a DAC, and an ADC. The sampling signal generator generates first and second sampling signals according to first and second reference clocks by a look-up table method, respectively. The DAC receives a digital input signal and converts it into an analog output signal according to the first sampling signal. The ADC receives an analog input signal and converts it into a digital output signal according to the second sampling signal.

Abstract: A P-tap parallel decision-feedback decoder (PDFD) is also disclosed. The PDFD includes a plurality of state shift registers. For each state of a code utilized by an incoming data stream, a survivor metric for a state is shifted into the first shift register for the state. Each first shift register has M cells. A decision device is coupled to the first shift registers for outputting a first survivor metric according to survivor metrics in the first shift registers. A second shift register has N delay cells, and the first survivor metric is shifted into the second shift register.

Abstract: A P-tap parallel decision-feedback decoder (PDFD) is also disclosed. The PDFD includes a plurality of state shift registers. For each state of a code utilized by an incoming data stream, a survivor metric for a state is shifted into the first shift register for the state. Each first shift register has M cells. A decision device is coupled to the first shift registers for outputting a first survivor metric according to survivor metrics in the first shift registers. A second shift register has N delay cells, and the first survivor metric is shifted into the second shift register.

Abstract: A DAC/ADC system for generating reference clocks for DAC/ADC by a look-up table method. The DAC/ADC system includes a sampling signal generator, a DAC, and an ADC. The sampling signal generator generates first and second sampling signals according to first and second reference clocks by a look-up table method, respectively. The DAC receives a digital input signal and converts it into an analog output signal according to the first sampling signal. The ADC receives an analog input signal and converts it into a digital output signal according to the second sampling signal.