Patents by Inventor Jung-Geun Jee

Jung-Geun Jee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110260234
    Abstract: A semiconductor device may include a tunnel insulating layer disposed on an active region of a substrate, field insulating patterns disposed in surface portions of the substrate to define the active region, each of the field insulating patterns having an upper recess formed at an upper surface portion thereof, a stacked structure disposed on the tunnel insulating layer, and impurity diffusion regions disposed at surface portions of the active region adjacent to the stacked structure.
    Type: Application
    Filed: June 29, 2011
    Publication date: October 27, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Hyun PARK, Jung-Geun Jee, Hyoeng-Ki Kim, Yong-Woo Hyung, Won-Jun Jang
  • Patent number: 8008214
    Abstract: In a method of forming an insulation structure, at least one oxide layer is formed on an object by at least one oxidation process, and then at least one nitride layer is formed from the oxide layer by at least one nitration process. An edge portion of the insulation structure may have a thickness substantially the same as that of a central portion of the insulation structure so that the insulation structure may have a uniform thickness and improved insulation characteristics. When the insulation structure is employed as a tunnel insulation layer of a semiconductor device, the semiconductor device may have enhanced endurance and improved electrical characteristics because a threshold voltage distribution of cells in the semiconductor device may become uniform.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: August 30, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Geun Jee, Young-Jin Noh, Bon-Young Koo, Chul-Sung Kim, Hun-Hyeoung Leam, Woong Lee
  • Patent number: 7972923
    Abstract: A semiconductor device may include a tunnel insulating layer disposed on an active region of a substrate, field insulating patterns disposed in surface portions of the substrate to define the active region, each of the field insulating patterns having an upper recess formed at an upper surface portion thereof, a stacked structure disposed on the tunnel insulating layer, and impurity diffusion regions disposed at surface portions of the active region adjacent to the stacked structure.
    Type: Grant
    Filed: November 29, 2006
    Date of Patent: July 5, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hyun Park, Jung-Geun Jee, Hyoeng-Ki Kim, Yong-Woo Hyung, Won-Jun Jang
  • Publication number: 20110101437
    Abstract: A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the active region and has an impurity ion concentration that becomes relatively low as the floating gate pattern gets nearer to the active region.
    Type: Application
    Filed: January 7, 2011
    Publication date: May 5, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Geun Jee, Ho-Min Son, Yong-Woo Hyung, Jae-Jong Han, Taek-Jin Lim
  • Patent number: 7888204
    Abstract: A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the active region and has an impurity ion concentration that becomes relatively low as the floating gate pattern gets nearer to the active region.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: February 15, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Geun Jee, Ho-Min Son, Yong-Woo Hyung, Jae-Jong Han, Taek-Jin Lim
  • Patent number: 7855117
    Abstract: In a method of forming a thin layer (e.g., a charge trapping nitride layer) of a semiconductor device (e.g. a charge trapping type non-volatile memory device), the nitride layer may be formed on a first area of a substrate. A blocking layer may be formed on the nitride layer. An oxide layer may be formed on a second area of the substrate while preventing or reducing an oxidation of the nitride layer by a radical oxidation process in which oxygen radicals react with the second area of the substrate and the blocking layer in the first area of the substrate. The nitride layer may ensure sufficient charge trapping sites and may have a uniform thickness without oxidation thereof in the radical oxidation process.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: December 21, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Jun Jang, Ho-Min Son, Woong Lee, Yong-Woo Hyung, Jung-Geun Jee
  • Publication number: 20100171166
    Abstract: A non-volatile memory device and a method of fabricating the same are provided. The method can include disposing an isolation layer on a semiconductor substrate. The isolation layer may protrude from the main surface of the semiconductor substrate and define an active region. In a recess defined by the protrusion of the isolation layer and the active region, a diffusion-retarding poly pattern and a floating gate may be formed in sequence. A control gate may be disposed on the isolation layer to cover the diffusion-retarding poly pattern and the floating gate.
    Type: Application
    Filed: December 30, 2009
    Publication date: July 8, 2010
    Inventors: Woong Lee, Jung-Yoon Ko, Sang-Kyoung Lee, Ho-Min Son, Won-Jun Jang, Jung-geun Jee
  • Patent number: 7585729
    Abstract: A method of manufacturing a non-volatile memory device, includes forming a tunnel isolation layer comprising an oxynitride on a substrate by a simultaneous oxidation and nitridation treatment in which an oxidation process and a nitridation process are simultaneously performed using a processing gas including oxygen and nitrogen. The method further includes performing first and second heat treatments to remove defect sites from the tunnel isolation layer in gas atmospheres including nitrogen (N) and chlorine (Cl), respectively and forming a gate structure on the tunnel isolation layer after the second heat treatment, and forming source/drain regions at surface portions of the substrate adjacent to the gate structure.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: September 8, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Kweon Baek, Bon-Young Koo, Chul-Sung Kim, Jung-Geun Jee, Young-Jin Noh
  • Publication number: 20090108323
    Abstract: A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the active region and has an impurity ion concentration that becomes relatively low as the floating gate pattern gets nearer to the active region.
    Type: Application
    Filed: August 15, 2008
    Publication date: April 30, 2009
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jung-Geun Jee, Ho-Min Son, Yong-Woo Hyung, Jae-Jong Han, Taek-Jin Lim
  • Patent number: 7410869
    Abstract: In a method of manufacturing a semiconductor device such as a flash memory device, an insulating pattern having an opening is formed to partially expose a surface of a substrate. A first silicon layer is formed on the exposed surface portion of the substrate and the insulating pattern. The first silicon layer has an opened seam overlying the previously exposed portion of the substrate. A heat treatment on the substrate is performed at a temperature sufficient to induce silicon migration so as to cause the opened seam to be closed via the silicon migration. A second silicon layer is then formed on the first silicon layer. Thus, surface profile of a floating gate electrode obtained from the first and second silicon layers may be improved.
    Type: Grant
    Filed: July 5, 2006
    Date of Patent: August 12, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hun-Hyeoung Leam, Hyeon-Deok Lee, Young-Sub You, Won-Jun Jang, Woong Lee, Jung-Hyun Park, Sang-Kyoung Lee, Jung-Geun Jee, Sang-Hoon Lee
  • Publication number: 20080105915
    Abstract: A semiconductor device may include a tunnel insulating layer disposed on an active region of a substrate, field insulating patterns disposed in surface portions of the substrate to define the active region, each of the field insulating patterns having an upper recess formed at an upper surface portion thereof, a stacked structure disposed on the tunnel insulating layer, and impurity diffusion regions disposed at surface portions of the active region adjacent to the stacked structure.
    Type: Application
    Filed: November 29, 2006
    Publication date: May 8, 2008
    Inventors: Jung-Hyun Park, Jung-Geun Jee, Hyoeng-Ki Kim, Yong-Woo Hyung, Won-Jun Jang
  • Publication number: 20080093657
    Abstract: A method of fabricating a nonvolatile memory device includes forming at least one insulating layer on at least one of a semiconductor substrate and a layer including a semi-conductive material, and performing a plasma process using fluorine on the semiconductor. In some cases, an interface between the insulating layer and the semiconductor substrate includes fluorine.
    Type: Application
    Filed: January 16, 2007
    Publication date: April 24, 2008
    Inventors: Ho-Min Son, Yong-Woo Hyung, Won-Jun Jang, Jung-Geun Jee, Hyoeng-Ki Kim
  • Publication number: 20080090354
    Abstract: A method of manufacturing a non-volatile memory device, includes forming a tunnel isolation layer comprising an oxynitride on a substrate by a simultaneous oxidation and nitridation treatment in which an oxidation process and a nitridation process are simultaneously performed using a processing gas including oxygen and nitrogen. The method further includes performing first and second heat treatments to remove defect sites from the tunnel isolation layer in gas atmospheres including nitrogen (N) and chlorine (Cl), respectively and forming a gate structure on the tunnel isolation layer after the second heat treatment, and forming source/drain regions at surface portions of the substrate adjacent to the gate structure.
    Type: Application
    Filed: October 5, 2007
    Publication date: April 17, 2008
    Inventors: Sung-Kweon Baek, Bon-Young Koo, Chul-Sung Kim, Jung-Geun Jee, Young-Jin Noh
  • Publication number: 20080064171
    Abstract: In a method of forming a thin layer (e.g., a charge trapping nitride layer) of a semiconductor device (e.g. a charge trapping type non-volatile memory device), the nitride layer may be formed on a first area of a substrate. A blocking layer may be formed on the nitride layer. An oxide layer may be formed on a second area of the substrate while preventing or reducing an oxidation of the nitride layer by a radical oxidation process in which oxygen radicals react with the second area of the substrate and the blocking layer in the first area of the substrate. The nitride layer may ensure sufficient charge trapping sites and may have a uniform thickness without oxidation thereof in the radical oxidation process.
    Type: Application
    Filed: October 31, 2006
    Publication date: March 13, 2008
    Inventors: Won-Jun Jang, Ho-Min Son, Woong Lee, Yong-Woo Hyung, Jung-Geun Jee
  • Publication number: 20080044981
    Abstract: Methods of fabricating semiconductor devices including forming a mask pattern on a semiconductor substrate are provided. The mask pattern defines a first opening that at least partially exposes the semiconductor substrate and includes a pad oxide layer and a nitride layer pattern on the pad oxide layer pattern. The nitride layer has a line width substantially larger than the pad oxide layer pattern. A second opening that is connected to the first opening is formed by at least partially removing a portion of the semiconductor substrate exposed through the first opening. The second opening has a sidewall that has a first inclination angle and at least partially exposing the semiconductor substrate. A trench connected to the second opening is formed by etching a portion of the semiconductor substrate exposed through the second opening using the mask pattern as an etch mask.
    Type: Application
    Filed: June 27, 2007
    Publication date: February 21, 2008
    Inventors: Jung Geun Jee, Won-Jun Jang, Woong Lee, Ho-Min Son, Won-Jun Lee, Hyoeng-Ki Kim, Jung-Hyun Park
  • Publication number: 20080014753
    Abstract: In a method of manufacturing a semiconductor device, a polysilicon layer doped with impurities is formed on a front side and a backside of a substrate. An insulation layer is formed on the substrate having the polysilicon layer to cover the polysilicon layer on the backside of the substrate. The insulation layer on the front side of the substrate is partially etched to partially expose the front side of the substrate. An oxidation process using oxygen radicals is then carried out to form an oxide layer on the exposed front side of the substrate Thus, when the oxidation process is carried out, the insulation layer prevents impurities in the polysilicon layer on the backside of the substrate from being outgassed. As a result electrical characteristics of the transistor formed on the front side of the substrate may not be deteriorated.
    Type: Application
    Filed: May 3, 2007
    Publication date: January 17, 2008
    Inventors: Won-Jun Jang, Yong-Woo Hyung, Jae-Jong Han, Ho-Min Son, Woong Lee, Jung-Geun Jee
  • Publication number: 20080014729
    Abstract: In a method of manufacturing a memory device, a tunnel insulation layer and a floating gate layer are formed on a semiconductor substrate. A top surface of the floating gate layer is converted into a first nitride layer by a first nitridation treatment process. The first nitride layer is converted into a first oxynitride layer by a radical oxidation process. A lower oxide layer is formed on the first oxynitride layer by an LPCVD process. A second nitride layer and an upper oxide layer are formed on the lower oxide layer. A conductive layer is formed on the upper oxide layer. Thus, a multi-layered dielectric layer including the first oxynitride layer, the lower oxide layer, the second nitride layer, the upper oxide layer and the densified second oxynitride layer may have an increased capacitance without having degenerated leakage current characteristics.
    Type: Application
    Filed: June 20, 2007
    Publication date: January 17, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Woong Lee, Jung-Geun Jee, Hyoeng-Ki Kim, Jung-Hyun Park, Ho-Min Son, Won-Jun Jang
  • Publication number: 20070167030
    Abstract: In a method of forming an insulation structure, at least one oxide layer is formed on an object by at least one oxidation process, and then at least one nitride layer is formed from the oxide layer by at least one nitration process. An edge portion of the insulation structure may have a thickness substantially the same as that of a central portion of the insulation structure so that the insulation structure may have a uniform thickness and improved insulation characteristics. When the insulation structure is employed as a tunnel insulation layer of a semiconductor device, the semiconductor device may have enhanced endurance and improved electrical characteristics because a threshold voltage distribution of cells in the semiconductor device may become uniform.
    Type: Application
    Filed: December 15, 2006
    Publication date: July 19, 2007
    Inventors: Jung-Geun Jee, Young-Jin Noh, Bon-Young Koo, Chul-Sung Kim, Hun-Hyeoung Leam, Woong Lee
  • Publication number: 20070026651
    Abstract: In a method of manufacturing a semiconductor device such as a flash memory device, an insulating pattern having an opening is formed to partially expose a surface of a substrate. A first silicon layer is formed on the exposed surface portion of the substrate and the insulating pattern. The first silicon layer has an opened seam overlying the previously exposed portion of the substrate. A heat treatment on the substrate is performed at a temperature sufficient to induce silicon migration so as to cause the opened seam to be closed via the silicon migration. A second silicon layer is then formed on the first silicon layer. Thus, surface profile of a floating gate electrode obtained from the first and second silicon layers may be improved.
    Type: Application
    Filed: July 5, 2006
    Publication date: February 1, 2007
    Inventors: Hun-Hyeoung Leam, Hyeon-Deok Lee, Young-Sub You, Won-Jun Jang, Woong Lee, Jung-Hyun Park, Sang-Kyoung Lee, Jung-Geun Jee, Sang-Hoon Lee