Patents by Inventor Jung Goo CHOI

Jung Goo CHOI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9681551
    Abstract: The present invention relates to a low temperature co-fired ceramic substrate with embedded capacitors. According to an embodiment of the present invention, the low temperature co-fired ceramic substrate with embedded capacitors is able to prevent diffusion, peeling or loss of electrodes after low temperature firing by controlling composition ratio of various metals included in the substrate, resulting in good adhesion between the ceramic substrate and the capacitor.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: June 13, 2017
    Assignee: SEMCNS CO., LTD.
    Inventors: Ji-Sung Na, Beom-Joon Cho, Jung-Goo Choi, Yun-Hwi Park, Kwang-Jae Oh, Ho-Sung Choo, Ji-Hwan Shin
  • Publication number: 20150122536
    Abstract: The present invention relates to a low temperature co-fired ceramic substrate with embedded capacitors. According to an embodiment of the present invention, the low temperature co-fired ceramic substrate with embedded capacitors is able to prevent diffusion, peeling or loss of electrodes after low temperature firing by controlling composition ratio of various metals included in the substrate, resulting in good adhesion between the ceramic substrate and the capacitor.
    Type: Application
    Filed: April 24, 2014
    Publication date: May 7, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ji-Sung NA, Beom-Joon CHO, Jung-Goo CHOI, Yun-Hwi PARK, Kwang-Jae OH, Ho-Sung CHOO, Ji-Hwan SHIN
  • Publication number: 20150028912
    Abstract: A board for a probe card includes a ceramic board including a first insulating layer, and second insulating layers disposed on one surface of the first insulating layer and including cavities for receiving electronic components, conductive patterns disposed on the first and second insulating layers, conductive vias electrically connecting the conductive patterns, and a capacitor disposed in the cavities. The cavities have a depth greater than a thickness of the capacitor to secure a space in a lower portion of the cavity after receiving the capacitor.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 29, 2015
    Inventors: Beom Joon CHO, Jung Goo CHOI, Ji Sung NA, Yun Hwi PARK, Kwang Jae OH, Ho Sung CHOO, Ji Hwan SHIN