Patents by Inventor Jung Goo Park
Jung Goo Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240117213Abstract: According to the present invention, there are provided a preparation method of a water-soluble acryl-modified phenolic-modified epoxy resin including preparing an acrylic copolymer resin containing a carboxylic acid group; preparing a phenolic-modified epoxy resin by reacting an epoxy resin with a phenolic compound; preparing an acryl-modified phenolic-modified epoxy resin by ester-reacting the acrylic copolymer resin with the phenolic-modified epoxy resin; and preparing a water-soluble acryl-modified phenolic-modified epoxy resin by neutralizing the acryl-modified phenolic-modified epoxy resin, a water-soluble acryl-modified phenolic-modified epoxy resin prepared thereby, and an aqueous paint composition including the same. According to the present invention, the water-soluble acryl-modified phenolic-modified epoxy resin and the aqueous coating composition including the same may be applied to most of conventional uses in which the epoxy resin is used due to excellent various physical properties.Type: ApplicationFiled: October 8, 2020Publication date: April 11, 2024Inventors: Myeng Chan HONG, Woo Jin SOHN, Jung Goo PARK
-
Patent number: 9502257Abstract: A non-volatile memory device and a method of manufacturing the non-volatile memory device, where the non-volatile memory device includes a floating gate insulating layer and a floating gate disposed on a substrate, a dielectric layer formed perpendicular to the floating gate insulating layer and at two sides of the floating gate, and a first control gate at a first side of the dielectric layer distal from the floating gate and a second control gate at a second side of the dielectric layer distal from the floating gate, wherein the first control gate and the second control gate are connected to each other, and a second width of the second control gate is wider than a first width of the first control gate. A length of a control gate of a non-volatile memory device may be extended to effectively preventing the generation of leakage current when a control gate is off.Type: GrantFiled: July 22, 2014Date of Patent: November 22, 2016Assignee: Magnachip Semiconductor, Ltd.Inventors: Jeong Ho Cho, Se Woon Kim, Kyung Min Kim, Jung Goo Park
-
Patent number: 9293750Abstract: A porous membrane contains a polyethylene resin, in a core layer, pores of sizes that are relatively larger than those of pores in each of skin layers on the opposite sides are distributed, and the skin layers on the opposite sides have substantially same pore characteristics. A method for manufacturing a porous membrane includes the steps of: obtaining a mixture of a liquid-type paraffin oil and a solid-type paraffin wax; adding the mixture to a polyethylene resin to obtain a raw material resin mixture; extruding and cooling the raw material resin mixture; stretching the raw material resin mixture; and immersing the stretched raw material resin mixture in an organic solvent to extract a mixture of the oil and the wax.Type: GrantFiled: October 5, 2012Date of Patent: March 22, 2016Assignee: W-Scope CorporationInventors: Jae Won Yang, Si Ju Ryu, Seong Tae Kim, Byung Hyunn Kim, Jung Goo Park, Hee Min Cho
-
Publication number: 20150311299Abstract: A non-volatile memory device and a method of manufacturing the non-volatile memory device, where the non-volatile memory device includes a floating gate insulating layer and a floating gate disposed on a substrate, a dielectric layer formed perpendicular to the floating gate insulating layer and at two sides of the floating gate, and a first control gate at a first side of the dielectric layer distal from the floating gate and a second control gate at a second side of the dielectric layer distal from the floating gate, wherein the first control gate and the second control gate are connected to each other, and a second width of the second control gate is wider than a first width of the first control gate. A length of a control gate of a non-volatile memory device may be extended to effectively preventing the generation of leakage current when a control gate is off.Type: ApplicationFiled: July 22, 2014Publication date: October 29, 2015Applicant: MAGNACHIP SEMICONDUCTOR, LTD.Inventors: Jeong Ho CHO, Se Woon KIM, Kyung Min KIM, Jung Goo PARK
-
Patent number: 9018735Abstract: A silicon wafer and fabrication method thereof are provided. The silicon wafer includes a first denuded zone formed with a predetermined depth from a top surface of the silicon wafer, the first denuded zone being formed with a depth ranging from approximately 20 ?m to approximately 80 ?m from the top surface, and a bulk area formed between the first denuded zone and a backside of the silicon wafer, the bulk area having a concentration of oxygen uniformly distributed within a variation of 10% over the bulk area.Type: GrantFiled: June 13, 2013Date of Patent: April 28, 2015Assignee: MagnaChip Semiconductor, Ltd.Inventor: Jung-Goo Park
-
Patent number: 8674427Abstract: A nonvolatile memory device and a method of manufacturing thereof are provided. The method includes forming a floating gate on a substrate, forming a dielectric layer to conform to a shape of the floating gate, forming a conductive layer to form a control gate on the substrate, the control gate covering the floating gate and the dielectric layer, forming a photoresist pattern on one side of the conductive layer, forming the control gate in the form of a spacer to surround sides of the floating gate, the forming of the control gate including performing an etch-back on the conductive layer until a portion of the dielectric layer on the floating gate is exposed, and forming a poly pad, to which a plurality of contact plugs are connected, on one side of the control gate, the forming of the poly pad including removing the photoresist pattern.Type: GrantFiled: May 11, 2012Date of Patent: March 18, 2014Assignee: Magnachip Semiconductor, Ltd.Inventors: Jeong-ho Cho, Jung-goo Park, Min-wan Chu, Doo-yeol Ryu
-
Publication number: 20130270681Abstract: A silicon wafer and fabrication method thereof are provided. The silicon wafer includes a first denuded zone formed with a predetermined depth from a top surface of the silicon wafer, the first denuded zone being formed with a depth ranging from approximately 20 ?m to approximately 80 ?m from the top surface, and a bulk area formed between the first denuded zone and a backside of the silicon wafer, the bulk area having a concentration of oxygen uniformly distributed within a variation of 10% over the bulk area.Type: ApplicationFiled: June 13, 2013Publication date: October 17, 2013Inventor: Jung-Goo PARK
-
Patent number: 8486813Abstract: A silicon wafer and fabrication method thereof are provided. The silicon wafer includes a first denuded zone formed with a predetermined depth from a top surface of the silicon wafer, the first denuded zone being formed with a depth ranging from approximately 20 ?m to approximately 80 ?m from the top surface, and a bulk area formed between the first denuded zone and a backside of the silicon wafer, the bulk area having a concentration of oxygen uniformly distributed within a variation of 10% over the bulk area.Type: GrantFiled: June 1, 2011Date of Patent: July 16, 2013Assignee: Magnachip Semiconductor, Ltd.Inventor: Jung-Goo Park
-
Publication number: 20130171499Abstract: A porous membrane contains a polyethylene resin, in a core layer, pores of sizes that are relatively larger than those of pores in each of skin layers on the opposite sides are distributed, and the skin layers on the opposite sides have substantially same pore characteristics. A method for manufacturing a porous membrane includes the steps of: obtaining a mixture of a liquid-type paraffin oil and a solid-type paraffin wax; adding the mixture to a polyethylene resin to obtain a raw material resin mixture; extruding and cooling the raw material resin mixture; stretching the raw material resin mixture; and immersing the stretched raw material resin mixture in an organic solvent to extract a mixture of the oil and the wax.Type: ApplicationFiled: October 5, 2012Publication date: July 4, 2013Inventors: Jae Won Yang, Si Ju Ryu, Seong Tae Kim, Byung Hyunn Kim, Jung Goo Park, Hee Min Cho
-
Publication number: 20130099301Abstract: A nonvolatile memory device and a method of manufacturing thereof are provided. The method includes forming a floating gate on a substrate, forming a dielectric layer to conform to a shape of the floating gate, forming a conductive layer to form a control gate on the substrate, the control gate covering the floating gate and the dielectric layer, forming a photoresist pattern on one side of the conductive layer, forming the control gate in the form of a spacer to surround sides of the floating gate, the forming of the control gate including performing an etch-back on the conductive layer until a portion of the dielectric layer on the floating gate is exposed, and forming a poly pad, to which a plurality of contact plugs are connected, on one side of the control gate, the forming of the poly pad including removing the photoresist pattern.Type: ApplicationFiled: May 11, 2012Publication date: April 25, 2013Applicant: MAGNACHIP SEMICONDUCTOR, LTD.Inventors: Jeong-ho Cho, Jung-goo Park, Min-wan Chu, Doo-yeol Ryu
-
Patent number: 8269281Abstract: Disclosed herein is a method for forming a triple gate oxide of a semiconductor device.Type: GrantFiled: November 16, 2010Date of Patent: September 18, 2012Assignee: Magnachip Semiconductor, Ltd.Inventor: Jung Goo Park
-
Publication number: 20110227202Abstract: A silicon wafer and fabrication method thereof are provided. The silicon wafer includes a first denuded zone formed with a predetermined depth from a top surface of the silicon wafer, the first denuded zone being formed with a depth ranging from approximately 20 ?m to approximately 80 ?m from the top surface, and a bulk area formed between the first denuded zone and a backside of the silicon wafer, the bulk area having a concentration of oxygen uniformly distributed within a variation of 10% over the bulk area.Type: ApplicationFiled: June 1, 2011Publication date: September 22, 2011Applicant: MAGNACHIP SEMICONDUCTOR, LTD.Inventor: Jung-Goo Park
-
Patent number: 7977216Abstract: Provided is a silicon wafer including: a first denuded zone formed with a predetermined depth from a top surface of the silicon wafer; and a bulk area formed between the first denuded zone and a backside of the silicon wafer, wherein the first denuded zone is formed with a depth ranging from approximately 20 um to approximately 80 um from the top surface, and wherein a concentration of oxygen in the bulk area is uniformly distributed within a variation of 10% over the bulk area.Type: GrantFiled: July 10, 2009Date of Patent: July 12, 2011Assignee: Magnachip Semiconductor, Ltd.Inventor: Jung-Goo Park
-
Publication number: 20110057252Abstract: Disclosed herein is a method for forming a triple gate oxide of a semiconductor device.Type: ApplicationFiled: November 16, 2010Publication date: March 10, 2011Inventor: JUNG GOO PARK
-
Patent number: 7892960Abstract: The method for forming a triple gate oxide of a semiconductor device includes the steps of defining a first region, a second region and a third region, forming a first oxide film and forming a second oxide film on the first oxide film, blocking the first region and selectively removing portions the second oxide film and the first oxide film, forming a third oxide film on the semiconductor substrate, blocking the first region and the second region and selectively removing a portion of the third oxide film and forming a fourth oxide film on the semiconductor substrate and then forming a nitride film thereon, wherein a gate oxide having a triple structure is formed in the first region, a gate oxide having a double structure is formed in the second region and a gate oxide having a double structure is formed in the third region.Type: GrantFiled: December 29, 2008Date of Patent: February 22, 2011Assignee: MagnaChip Semiconductor, Ltd.Inventor: Jung Goo Park
-
Publication number: 20100078767Abstract: Provided is a silicon wafer including: a first denuded zone formed with a predetermined depth from a top surface of the silicon wafer; and a bulk area formed between the first denuded zone and a backside of the silicon wafer, wherein the first denuded zone is formed with a depth ranging from approximately 20 um to approximately 80 um from the top surface, and wherein a concentration of oxygen in the bulk area is uniformly distributed within a variation of 10 % over the bulk area.Type: ApplicationFiled: July 10, 2009Publication date: April 1, 2010Inventor: Jung-Goo PARK
-
Publication number: 20090179255Abstract: The method for forming a triple gate oxide of a semiconductor device includes the steps of defining a first region, a second region and a third region, forming a first oxide film and forming a second oxide film on the first oxide film, blocking the first region and selectively removing portions the second oxide film and the first oxide film, forming a third oxide film on the semiconductor substrate, blocking the first region and the second region and selectively removing a portion of the third oxide film and forming a fourth oxide film on the semiconductor substrate and then forming a nitride film thereon, wherein a gate oxide having a triple structure is formed in the first region, a gate oxide having a double structure is formed in the second region and a gate oxide having a double structure is formed in the third region.Type: ApplicationFiled: December 29, 2008Publication date: July 16, 2009Inventor: Jung Goo Park