Patents by Inventor Jung H. Yoon
Jung H. Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10886004Abstract: A computer-implemented method for sorting non-volatile random access memories (NVRAMS) includes testing a failure metric for each of a plurality of NVRAMS over a plurality of testing sessions to capture failure metric data that corresponds to the plurality of NVRAMS. The method also includes determining a trend in the failure metric as a function of testing cycles for each of the plurality of NVRAMS from the failure metric data, and separating the plurality of NVRAMS into groups based on the trend in the failure metric as a function of testing cycles. A corresponding computer program product and computer system are also disclosed herein.Type: GrantFiled: July 24, 2019Date of Patent: January 5, 2021Assignee: International Business Machines CorporationInventors: Jeffrey W. Christensen, Phillip E. Christensen, Daniel E. Moore, Antoine G. Sater, Jung H. Yoon
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Patent number: 10810345Abstract: A computer-implemented method modifies a manufacturing process for integrated circuits that include memory chips and a memory buffer. One or more processors identify a performance trending estimate of memory chip failures versus memory buffer failures in failed integrated circuits. The processor(s) identify a location and address of each memory chip in the identified failed integrated circuits that has a memory chip failure. The processor(s) identify a wafer location on a wafer die on which each memory buffer that has a memory buffer failure was formed. The processor(s) predict a fault analysis (FA) pareto based on the performance trending estimate, the location and address of each memory chip in the failed integrated circuits, and the wafer location on the wafer die on which each memory buffer that has the memory buffer failure was formed such that a manufacturing process for the integrated circuits is modified based on the FA pareto.Type: GrantFiled: April 17, 2019Date of Patent: October 20, 2020Assignee: International Business Machines CorporationInventors: Steven B. Gold, Wen Wei Low, Feng Xue, Yvonne Chii Yeo, Jung H. Yoon
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Publication number: 20190348144Abstract: A computer-implemented method for sorting non-volatile random access memories (NVRAMS) includes testing a failure metric for each of a plurality of NVRAMS over a plurality of testing sessions to capture failure metric data that corresponds to the plurality of NVRAMS. The method also includes determining a trend in the failure metric as a function of testing cycles for each of the plurality of NVRAMS from the failure metric data, and separating the plurality of NVRAMS into groups based on the trend in the failure metric as a function of testing cycles. A corresponding computer program product and computer system are also disclosed herein.Type: ApplicationFiled: July 24, 2019Publication date: November 14, 2019Inventors: Jeffrey W. Christensen, Phillip E. Christensen, Daniel E. Moore, Antoine G. Sater, Jung H. Yoon
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Patent number: 10460825Abstract: A computer-implemented method for sorting non-volatile random access memories (NVRAMS) includes testing a failure metric for each of a plurality of NVRAMS over a plurality of testing sessions to capture failure metric data that corresponds to the plurality of NVRAMS. The method also includes determining a trend in the failure metric as a function of testing cycles for each of the plurality of NVRAMS from the failure metric data, and separating the plurality of NVRAMS into groups based on the trend in the failure metric as a function of testing cycles. A corresponding computer program product and computer system are also disclosed herein.Type: GrantFiled: January 28, 2016Date of Patent: October 29, 2019Assignee: International Business Machines CorporationInventors: Jeffrey W. Christensen, Phillip E. Christensen, Daniel E. Moore, Antoine G. Sater, Jung H. Yoon
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Publication number: 20190243941Abstract: A computer-implemented method modifies a manufacturing process for integrated circuits that include memory chips and a memory buffer. One or more processors identify a performance trending estimate of memory chip failures versus memory buffer failures in failed integrated circuits. The processor(s) identify a location and address of each memory chip in the identified failed integrated circuits that has a memory chip failure. The processor(s) identify a wafer location on a wafer die on which each memory buffer that has a memory buffer failure was formed. The processor(s) predict a fault analysis (FA) pareto based on the performance trending estimate, the location and address of each memory chip in the failed integrated circuits, and the wafer location on the wafer die on which each memory buffer that has the memory buffer failure was formed such that a manufacturing process for the integrated circuits is modified based on the FA pareto.Type: ApplicationFiled: April 17, 2019Publication date: August 8, 2019Inventors: STEVEN B. GOLD, WEN WEI LOW, FENG XUE, YVONNE CHII YEO, JUNG H. YOON
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Patent number: 10318700Abstract: A computer-implemented method modifies a manufacturing process for integrated circuits. One or more processors receive sensor readings that identify failed integrated circuits from a batch of integrated circuits, where each of the integrated circuits includes a set of dynamic random access memory (DRAM) chips and a memory buffer, where the memory buffer provides an interface between a memory controller and the DRAM chips. The processor(s) identify, based on the sensor readings, a performance trending estimate of DRAM failures versus memory buffer failures in the identified failed integrated circuits. The processor(s) predict a fault analysis (FA) pareto based on the performance trending estimate, a location and address of each DRAM in the identified failed integrated circuits, and a wafer location on the wafer die on which each memory buffer that has the memory buffer failure, such that a manufacturing process for the integrated circuits is modified based on the FA pareto.Type: GrantFiled: September 5, 2017Date of Patent: June 11, 2019Assignee: International Business Machines CorporationInventors: Steven B. Gold, Wen Wei Low, Feng Xue, Yvonne Chii Yeo, Jung H. Yoon
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Publication number: 20190073442Abstract: A computer-implemented method modifies a manufacturing process for integrated circuits. One or more processors receive sensor readings that identify failed integrated circuits from a batch of integrated circuits, where each of the integrated circuits includes a set of dynamic random access memory (DRAM) chips and a memory buffer, where the memory buffer provides an interface between a memory controller and the DRAM chips. The processor(s) identify, based on the sensor readings, a performance trending estimate of DRAM failures versus memory buffer failures in the identified failed integrated circuits. The processor(s) predict a fault analysis (FA) pareto based on the performance trending estimate, a location and address of each DRAM in the identified failed integrated circuits, and a wafer location on the wafer die on which each memory buffer that has the memory buffer failure, such that a manufacturing process for the integrated circuits is modified based on the FA pareto.Type: ApplicationFiled: September 5, 2017Publication date: March 7, 2019Inventors: STEVEN B. GOLD, WEN WEI LOW, FENG XUE, YVONNE CHII YEO, JUNG H. YOON
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Publication number: 20170221586Abstract: A computer-implemented method for sorting non-volatile random access memories (NVRAMS) includes testing a failure metric for each of a plurality of NVRAMS over a plurality of testing sessions to capture failure metric data that corresponds to the plurality of NVRAMS. The method also includes determining a trend in the failure metric as a function of testing cycles for each of the plurality of NVRAMS from the failure metric data, and separating the plurality of NVRAMS into groups based on the trend in the failure metric as a function of testing cycles. A corresponding computer program product and computer system are also disclosed herein.Type: ApplicationFiled: December 5, 2016Publication date: August 3, 2017Inventors: Jeffrey W. Christensen, Phillip E. Christensen, Daniel E. Moore, Antoine G. Sater, Jung H. Yoon
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Publication number: 20170221587Abstract: A computer-implemented method for sorting non-volatile random access memories (NVRAMS) includes testing a failure metric for each of a plurality of NVRAMS over a plurality of testing sessions to capture failure metric data that corresponds to the plurality of NVRAMS. The method also includes determining a trend in the failure metric as a function of testing cycles for each of the plurality of NVRAMS from the failure metric data, and separating the plurality of NVRAMS into groups based on the trend in the failure metric as a function of testing cycles. A corresponding computer program product and computer system are also disclosed herein.Type: ApplicationFiled: December 5, 2016Publication date: August 3, 2017Inventors: Jeffrey W. Christensen, Phillip E. Christensen, Daniel E. Moore, Antoine G. Sater, Jung H. Yoon
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Publication number: 20170221582Abstract: A computer-implemented method for sorting non-volatile random access memories (NVRAMS) includes testing a failure metric for each of a plurality of NVRAMS over a plurality of testing sessions to capture failure metric data that corresponds to the plurality of NVRAMS. The method also includes determining a trend in the failure metric as a function of testing cycles for each of the plurality of NVRAMS from the failure metric data, and separating the plurality of NVRAMS into groups based on the trend in the failure metric as a function of testing cycles. A corresponding computer program product and computer system are also disclosed herein.Type: ApplicationFiled: January 28, 2016Publication date: August 3, 2017Inventors: Jeffrey W. Christensen, Phillip E. Christensen, Daniel E. Moore, Antoine G. Sater, Jung H. Yoon
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Patent number: 9530522Abstract: A computer-implemented method for sorting non-volatile random access memories (NVRAMS) includes testing a failure metric for each of a plurality of NVRAMS over a plurality of testing sessions to capture failure metric data that corresponds to the plurality of NVRAMS. The method also includes determining a trend in the failure metric as a function of testing cycles for each of the plurality of NVRAMS from the failure metric data, and separating the plurality of NVRAMS into groups based on the trend in the failure metric as a function of testing cycles. A corresponding computer program product and computer system are also disclosed herein.Type: GrantFiled: March 10, 2016Date of Patent: December 27, 2016Assignee: International Business Machines CorporationInventors: Jeffrey W. Christensen, Phillip E. Christensen, Daniel E. Moore, Antoine G. Sater, Jung H. Yoon
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Patent number: 9286585Abstract: A method for determining quality includes receiving supplier quality data from a supplier. The supplier quality data includes discrete quality data. The supplier quality data is for a quantity of a component supplied to a company or for a service provided on behalf of the company over a supplier measurement period. The method includes aggregating quality data from two or more suppliers. The quality data is for the supplied component or provided service over a baseline time period. The method includes determining a quality benchmark using the aggregated quality data and setting one or more alarm levels. The alarm levels are based on the quality benchmark of the aggregated quality data. The method includes determining supplier quality level for the supplier for the supplier measurement time period. The supplier quality is based on the supplier quality data. The method includes determining if the supplier quality data exceeds an alarm level.Type: GrantFiled: October 26, 2012Date of Patent: March 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert A DiMarco, Vincent J Giancaspro, Michael J Whitney, Feng Xue, Jung H Yoon
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Patent number: 9081758Abstract: An approach to determine a power-on-hour offset for a memory device that is newly-installed into a computer system is provided, which subtracts a current power-on-hour count of the memory device from a current power-on-hour value of a power supply that supplies operative power to the memory device within the computer system. In response to the computer system powering down, an accumulated power-on-hour for the memory device is determined by subtracting the power-on-hour offset of the memory from a current power-on-hour value of the computer system power supply. The determined power-on-hour offset and accumulated power-on-hour values are saved into one or more designated bytes of a free area of electrically erasable programmable read-only memory of the memory device that are available for data storage by a memory controller, and wherein data stored therein persists after operative power is lost to the memory device, the memory controller or the computer system.Type: GrantFiled: August 18, 2014Date of Patent: July 14, 2015Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.Inventors: Tu To Dang, Juan Q. Hernandez, Sumeet Kochar, Jung H. Yoon
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Patent number: 8990479Abstract: An approach to determine a power-on-hour offset for a memory device that is newly-installed into a computer system is provided, which subtracts a current power-on-hour count of the memory device from a current power-on-hour value of a power supply that supplies operative power to the memory device within the computer system. In response to the computer system powering down, an accumulated power-on-hour for the memory device is determined by subtracting the power-on-hour offset of the memory from a current power-on-hour value of the computer system power supply. The determined power-on-hour offset and accumulated power-on-hour values are saved into one or more designated bytes of a free area of electrically erasable programmable read-only memory of the memory device that are available for data storage by a memory controller, and wherein data stored therein persists after operative power is lost to the memory device, the memory controller or the computer system.Type: GrantFiled: July 30, 2012Date of Patent: March 24, 2015Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.Inventors: Tu To Dang, Juan Q. Hernandez, Sumeet Kochar, Jung H. Yoon
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Publication number: 20150006967Abstract: An approach to determine a power-on-hour offset for a memory device that is newly-installed into a computer system is provided, which subtracts a current power-on-hour count of the memory device from a current power-on-hour value of a power supply that supplies operative power to the memory device within the computer system. In response to the computer system powering down, an accumulated power-on-hour for the memory device is determined by subtracting the power-on-hour offset of the memory from a current power-on-hour value of the computer system power supply. The determined power-on-hour offset and accumulated power-on-hour values are saved into one or more designated bytes of a free area of electrically erasable programmable read-only memory of the memory device that are available for data storage by a memory controller, and wherein data stored therein persists after operative power is lost to the memory device, the memory controller or the computer system.Type: ApplicationFiled: August 18, 2014Publication date: January 1, 2015Inventors: Tu To Dang, John Q. Hernandez, Sumeet Kochar, Jung H. Yoon
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Publication number: 20140121805Abstract: A method for determining quality includes receiving supplier quality data from a supplier. The supplier quality data includes discrete quality data. The supplier quality data is for a quantity of a component supplied to a company or for a service provided on behalf of the company over a supplier measurement period. The method includes aggregating quality data from two or more suppliers. The quality data is for the supplied component or provided service over a baseline time period. The method includes determining a quality benchmark using the aggregated quality data and setting one or more alarm levels. The alarm levels are based on the quality benchmark of the aggregated quality data. The method includes determining supplier quality level for the supplier for the supplier measurement time period. The supplier quality is based on the supplier quality data. The method includes determining if the supplier quality data exceeds an alarm level.Type: ApplicationFiled: October 26, 2012Publication date: May 1, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert A. DiMarco, Vincent J. Giancaspro, Michael J. Whitney, Feng Xue, Jung H. Yoon
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Publication number: 20140032819Abstract: An approach to determine a power-on-hour offset for a memory device that is newly-installed into a computer system is provided, which subtracts a current power-on-hour count of the memory device from a current power-on-hour value of a power supply that supplies operative power to the memory device within the computer system. In response to the computer system powering down, an accumulated power-on-hour for the memory device is determined by subtracting the power-on-hour offset of the memory from a current power-on-hour value of the computer system power supply. The determined power-on-hour offset and accumulated power-on-hour values are saved into one or more designated bytes of a free area of electrically erasable programmable read-only memory of the memory device that are available for data storage by a memory controller, and wherein data stored therein persists after operative power is lost to the memory device, the memory controller or the computer system.Type: ApplicationFiled: July 30, 2012Publication date: January 30, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tu To Dang, Juan Q. Hernandez, Sumeet Kochar, Jung H. Yoon
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Patent number: 7612446Abstract: A spring-like cooling structure for an in-line chip module is formed from a continuous sheet of a thermally conducting material having a front side and a back side, the sheet folded at substantially a one-hundred and eighty degree angle, wherein a length of the structure substantially correlates to a length of the in-line chip module, and a width of the structure is wider than a width of the in-line chip module such that the structure fits over and substantially around the in-line chip module; openings at a left-side, right-side and a bottom of the structure for easily affixing and removing the structure from the in-line chip module; a top part comprising a top surface disposed over a top of the in-line chip module when affixed to the in-line chip module, and comprising an angled surface flaring outward from the in-line chip module, the angled surface positioned directly beneath the top surface; a center horizontal part; a gap between the center horizontal part and the plurality of chips; and a flared bottomType: GrantFiled: November 22, 2006Date of Patent: November 3, 2009Assignee: International Business Machines CorporationInventors: Hien P. Dang, Vinod Kamath, Vijayeshwar D. Khanna, Gerard McVicker, Sri M. Sri-Jayantha, Jung H. Yoon
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Publication number: 20080116571Abstract: A spring-like cooling structure for an in-line chip module is formed from a continuous sheet of a thermally conducting material having a front side and a back side, the sheet folded at substantially a one-hundred and eighty degree angle, wherein a length of the structure substantially correlates to a length of the in-line chip module, and a width of the structure is wider than a width of the in-line chip module such that the structure fits over and substantially around the in-line chip module; openings at a left-side, right-side and a bottom of the structure for easily affixing and removing the structure from the in-line chip module; a top part comprising a top surface disposed over a top of the in-line chip module when affixed to the in-line chip module, and comprising an angled surface flaring outward from the in-line chip module, the angled surface positioned directly beneath the top surface; a center horizontal part; a gap between the center horizontal part and the plurality of chips; and a flared bottomType: ApplicationFiled: November 22, 2006Publication date: May 22, 2008Applicant: International Business Machines Corporation, Inc.Inventors: Hien P. Dang, Vinod Kamath, Vijayeshwar D. Khanna, Gerard McVicker, Sri M. Sri-Jayantha, Jung H. Yoon
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Patent number: 6869899Abstract: The invention relates generally to lithographic patterning of very small features. In particular, the invention relates generally to patterning of semiconductor circuit features smaller than lithographically defined using either conventional optical lithography or next generation lithography techniques. The invention relates more particularly, but not by way of limitation, to lateral trimming of photoresist images.Type: GrantFiled: July 12, 2001Date of Patent: March 22, 2005Assignee: International Business Machines CorporationInventors: Arpan P. Mahorowala, Maheswaran Surendra, Jung H. Yoon, Ying Zhang