Abstract: A light-emitting element includes a first semiconductor layer, a light-emitting layer disposed on the first semiconductor layer, a second semiconductor layer disposed on the light-emitting layer, a device electrode layer disposed on the second semiconductor layer, a reflective electrode layer disposed on the device electrode layer, an insulating film surrounding a side surface of the light-emitting layer, a side surface of the second semiconductor layer, and a side surface of the device electrode layer, and a reflective layer surrounding a side surface of the insulating film, wherein the side surface of the device electrode layer is aligned with a side surface of the reflective electrode layer.

Abstract: An optical sheet includes a substrate onto which light is incident, and a convex part protruded from the substrate by a predetermined thickness. A thickness of the convex part increases from an edge to a center thereof.

Abstract: An optical sheet includes a substrate onto which light is incident, and a convex part protruded from the substrate by a predetermined thickness. A thickness of the convex part increases from an edge to a center thereof.

Abstract: An optical sheet includes a substrate onto which light is incident, and a convex part protruded from the substrate by a predetermined thickness. A thickness of the convex part increases from an edge to a center thereof.

Abstract: Clock gating circuits are disclosed in the present disclosure. Also disclosed herein are methods for designing clock gating circuits in the early stages of manufacturing. In one embodiment of a method for designing a clock gating circuit, the method comprises providing a schematic layout of a D-type flip-flop, wherein the flip-flop has a reset terminal and two latches. The method further comprises modifying the layout of the flip-flop to create a clock gating circuit.

Abstract: In a multi-port register file of a storage unit within a processor, an improved bitcell design for storing a data bit is disclosed. The bitcell comprises a first set of read bitlines having a first load and a second set of read bitlines having a second load, in which the second load is substantially equal to the first load. The bitcell also comprises a signal driving circuit having a first node and a second node. The first node is connected to the first set of read bitlines and the second node is connected to the second set of read bitlines.

Abstract: Clock gating circuits are disclosed in the present disclosure. Also disclosed herein are methods for designing clock gating circuits in the early stages of manufacturing. In one embodiment of a method for designing a clock gating circuit, the method comprises providing a schematic layout of a D-type flip-flop, wherein the flip-flop has a reset terminal and two latches. The method further comprises modifying the layout of the flip-flop to create a clock gating circuit.