Abstract: Disclosed is an operating method of a direct memory access (DMA) controller having first and second DMA channels. The operating method includes iteratively performing a DMA transfer operation of the first DMA channel based upon loop information and transfer information of the first DMA channel; iteratively performing a DMA transfer operation of the second DMA channel based upon loop information and transfer information of the second DMA channel; reconfiguring the transfer and loop information of the first and second DMA channels; and again performing the iteratively performing a DMA transfer operation of the first DMA channel and the iteratively performing a DMA transfer operation of the first DMA channel based upon the reconfigured transfer and loop information of the first and second DMA channels.

Abstract: Disclosed is a structure of an adaptive multimedia processor and a method for implementing an adaptive data processing algorithm. The adaptive multimedia processor includes a bit stream analyzer for analyzing bit stream information of multimedia data, and a bit stream learning device for converting multimedia data having a format which cannot be reproduced in a device, to multimedia data having a format which can be reproduced in a device, through an execution of a learning algorithm, based on an analysis by the bit stream analyzer.

Abstract: Provided is an image matching method of matching at least two images. The image matching method extracts feature points of a reference image and feature points of a target image, changes a feature point, selected from among the feature points of the reference image, to a reference point in the target image, sets a matching candidate region on the basis of the reference point, in the target image, and performs a similarity operation between the selected feature point in the reference image and a plurality of feature points included in the matching candidate region among the feature points of the target image. The image matching method decreases the number of similarity operations performed in the image matching operation, thereby guaranteeing a high-speed operation.

Abstract: Provided are an object detection device and system. The object detection device includes an outline image extraction unit, a feature vector calculation unit, and an object judgment unit. The outline image extraction unit extracts an outline image from an input image. The feature vector calculation unit calculates a feature vector from the outline image by using histogram of oriented gradients (HOG) representing a frequency distribution of gradient vectors with respect to pixels of the outline image, and pixel coordinate information varying according to a spatial distribution of the gradient vectors. The object judgment unit judges a target object corresponding to the feature vector with reference to pre-learned data.

Abstract: Provided is a low power consumption processor. The processor includes: a plurality of blocks; a memory storing instructions that control each of the plurality of blocks; and a multi power controller generates a signal that activates at least one of the plurality of blocks according to an address storing the instruction, and provides a normal power voltage or a reduction power voltage in response to the activation signal.

Abstract: Provided is an image recognizing method. The image recognizing method includes selecting a partial data from a standard image data, recognizing image based on the selected data, reduction-converting the selected data, and recognizing image based on the reduction-converted data.

Abstract: Provided is a vector classifier and a vector classification method. The vector classifier includes a vector compressor configured to compress an input vector; a support vector storage unit configured to store a compressed support vector; and a support vector machine operation unit configured to receive the compressed input vector and the compressed support vector and perform an arithmetic operation according to a classification determining equation.

Abstract: The obstacle detecting system includes a first image acquiring unit which acquires first image information by selectively receiving a laser beam emitted from at least one laser source toward a road surface at a target distance; a second image acquiring unit which acquires an image of actual surroundings as second image information; an image recognizing unit which recognizes an image of an obstacle by performing 3-D image recognition signal processing on line information of the laser beam using the first image information, and recognizes a pattern of the obstacle by performing pattern recognition signal processing on the second image information; and a risk determining unit which determines a possibility of collision due to presence of the obstacle within the target distance by classifying the recognized obstacles according to whether or not the image-recognized obstacle is matched with the pattern-recognized obstacle.

Abstract: Provided are a reconfigurable arithmetic unit and a processor having the same. The reconfigurable arithmetic unit can perform an addition operation or a multiplication operation according to an instruction by sharing an adder. The reconfigurable arithmetic unit includes a booth encoder for encoding a multiplier, a partial product generator for generating a plurality of partial products using the encoded multiplier and a multiplicand, a Wallace tree circuit for compressing the partial products into a first partial product and a second partial product, a first Multiplexer (MUX) for selecting and outputting one of the first partial product and a first addition input according to a selection signal, a second MUX for selecting and outputting one of the second partial product and a second addition input according to the selection signal, and a Carry Propagation Adder (CPA) for adding an output of the first MUX and an output of the second MUX to output an operation result.

Abstract: Provided are a system and method for detecting an object. The method includes selecting a macroscopic scan mode in which there are a small number of divided regions or a microscopic scan mode in which there are a large number of divided regions according to complexity of a background including an object to be detected, dividing an input image into one or more regions according to the selected scan mode, merging adjacent regions having similar characteristics among the divided regions, extracting a search region by excluding a region having a high probability that the object to be detected does not exist from the divided or merged regions, extracting feature data including a feature vector for detecting the object in the search region, and detecting the object in the search region using the extracted feature data.

Abstract: Provided is a direct memory access (DMA) controller. The DMA controller includes a plurality of channel groups and a channel group controller. Each of the channel groups has a plurality of DMA channels, and the channel group controller controls enablement of the DMA channels in units of channel groups. Herein, the channel group controller enables the DMA channels of at least one of the channel groups in data transmission.

Abstract: An apparatus and method for decoding moving images based on parallel processing are provided. The apparatus for decoding images based on parallel processing can improve operational performance by pipelining massive-data transmission between processors while performing context-adaptive variable length decoding (CAVLD), inverse quantization (IQ), inverse transformation (IT), motion compensation (MC), intra prediction (IP) and deblocking filter (DF) operations in parallel in units of pluralities of macroblocks (MBs).

Abstract: Provided are an apparatus and method for recognizing an image. In the apparatus and method for recognizing an image, various features can be extracted by a Haar-like filter using 1st to nth order gradients of the x- and y-axis of an input image, and the input image is correctly classified as a true or false image using, in stages, the extracted features of the input image, multiple threshold values for a true image and multiple threshold values for a false image. Accordingly, the apparatus and method achieve a high recognition rate by performing a small amount of computation. Consequently, it is possible to rapidly and correctly recognize an image, enabling real-time image recognition.

Abstract: The present invention provides an apparatus and method for predicting a moving direction of another vehicle running on a carriageway adjacent to a user's vehicle using periodically acquired image information around the user's vehicle, and performing a control process of preventing collision of the user's vehicle when a moving direction of the user's vehicle crosses the moving direction of the other vehicle.

Abstract: According to the present invention, the amount of computation required for image recognition processing can be reduced by extracting only image recognition learning information for an object that may appear in a region having the geographical property of a current position and comparing the image recognition learning information with ambient-image information.

Abstract: Provided is a bit stream processor using a reduced table lookup. The bit stream processor includes a bit stream exclusive register in a general purpose register in order to process data of a variable length effectively. Additionally, the bit stream processor an instruction of a table lookup method to which a prefix method is applied and a bit stream exclusive instruction in order to reduce an entire memory size.

Abstract: Provided is an apparatus for calculating an absolute difference capable of efficiently performing an absolute difference using an adder. The apparatus for calculating an absolute difference includes a comparator comparing values of two integers, first and second selectors each selecting and outputting one of the two integers according to the comparison results of the comparator, an inverter complementing the result value selected by the second selector; and an adder adding up the result value selected by the first selector, the value complemented by the inverter, and 1.

Abstract: Provided is a direct memory access (DMA) controller having an interrupt control processor that can process DMA transmission-related interrupts according to a control program modifiable by a user. The DMA controller includes the interrupt control processor that can process a DMA transmission-related interrupt and a DMA request interrupt transmitted from peripheral devices and control the DMA channel through the control program that can be modified by the user, so that DMA channel control and relevant interrupt processing loads caused by a plurality of DMA data transmissions are reduced, and the flexibility of DMA channel control and interrupt processing in control of the DMA controller is provided to the user.

Abstract: Provided is a data processing circuit. A control unit outputs an operation control signal and a memory control signal. A plurality of program memories each outputs a command in response to the memory control signal. A plurality of arithmetic sections each selectively performs any one of the commands from the plurality of program memories in response to the operation control signal. Operation modes of the data processing circuit can be flexibly changed according to operation environments.

Abstract: Provided is a bit stream processor using a reduced table lookup. The bit stream processor includes a bit stream exclusive register in a general purpose register in order to process data of a variable length effectively. Additionally, the bit stream processor an instruction of a table lookup method to which a prefix method is applied and a bit stream exclusive instruction in order to reduce an entire memory size.