Abstract: An electronic device is provided. The electronic device may include a display, a processor operatively connected with the display and configured to generate external reference time information, a display driver integrated circuit configured to periodically or randomly receive the external reference time information from the processor, wherein the display driver integrated circuit is configured to generate internal time information based on an internal clock, to output a clock image corresponding to the internal time information on the display, and if a time error between the external reference time information and the internal time information occurs during the outputting of the clock image, to output the internal time information, the time error of which is corrected, on the display.

Abstract: An electronic device is provided. The electronic device may include a display, a processor operatively connected with the display and configured to generate external reference time information, a display driver integrated circuit configured to periodically or randomly receive the external reference time information from the processor, wherein the display driver integrated circuit is configured to generate internal time information based on an internal clock, to output a clock image corresponding to the internal time information on the display, and if a time error between the external reference time information and the internal time information occurs during the outputting of the clock image, to output the internal time information, the time error of which is corrected, on the display.

Abstract: An electronic device is provided. The electronic device may include a display, a processor operatively connected with the display and configured to generate external reference time information, a display driver integrated circuit configured to periodically or randomly receive the external reference time information from the processor, wherein the display driver integrated circuit is configured to generate internal time information based on an internal clock, to output a clock image corresponding to the internal time information on the display, and if a time error between the external reference time information and the internal time information occurs during the outputting of the clock image, to output the internal time information, the time error of which is corrected, on the display.

Abstract: A display driver circuit can include an input selector circuit configured to receive first display data from a high power processor circuit and configured to operate in a normal mode in which the first display data is provided and in a dormant mode in which no image data is provided to the input selector circuit and configured to receive second display data from a low power processor circuit that is configured provide the second display data when the high power processor circuit is in the dormant mode. A controller circuit, can be coupled to switch the first display data or the second display data through the input selector circuit based on the mode of operation of the high power processor circuit.

Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.

Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.

Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.

Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.

Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.

Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.

Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.

Abstract: A method of erasing a flash memory according to the present invention includes the steps of: performing a first loop erasing operation so that a source electrode is floated, a program gate electrode is applied with a negative voltage and a drain electrode is supplied with an initial erasing voltage; and performing a second loop erasing operation so that the source electrode is floated, the program gate electrode is applied with the negative voltage and the drain electrode is supplied with a normal erasing voltage higher than the initial erasing voltage.

Abstract: The present invention relates to the charge pump circuit and, more particularly to the charge pump circuit which can decrease the time period of voltage rise of the charge pump circuit by making the charge pumping voltage outputted from the output stage of the pump circuit section to be satisfactorily supplied to the load section, by making the rate of the gate voltage rise of the voltage drop transistor to be higher than the rate of drain voltage rise.