Abstract: The present invention provides a system and method for automatically controlling the phase of the clock signal for sampling an HDTV signal, which implements a new and improved method for phase detection. The system and method utilize the standard format of an HDTV signal to consistently ensure accurate phase detection. Particularly, the system and method detect the target phase for the sampling clock using a tri-level sync pattern that exists at the beginning of each display line. This tri-level sync pattern or “sync pulse” is well suited for phase detection since it includes several static areas separated by substantial transitions. Furthermore, by using the sync pulse of the HDTV signal, the system and method provide consistent and accurate results, since the sync pulse will not change regardless of the whether the video data is static or in motion.

Abstract: Apparatus and methods for a cache controller to maintain cache consistency in a cache memory structure having a single copy of a cache tag memory while supporting multiple outstanding operations in a multiple processor computer system. The CPU includes a small internal cache memory structure. A substantially larger external cache array is coupled to both the CPU and the CC via first, integrated address and data bus. The CC is in turn coupled to a second bus interconnecting, among other devices, processors, I/O devices, and a main memory. The external cache is subblocked. A cache directory in the CC tracks usage of the external cache. An input buffer in the CC is connected to the first bus to provide buffering of commands sent by the CPUs. An output buffer in the CC is coupled to the second bus for buffering commands directed by the CC to devices operating on the second bus.

Abstract: Apparatus and methods for a cache controller preserving cache consistency and providing multiple outstanding operations in a cache memory structure supporting a high performance central processor unit (CPU). An external cache array is coupled to both the CPU and a cache controller (CC), and is subblocked to reduce miss rate. The CC is coupled via a high speed bus to a main memory. A cache directory in the CC tracks usage of the external cache, and is organized to support a choice of bus protocols for buses intercoupling the CC to the main memory. The cache directory consists of tag entries, each tag entry having an address field and multiple status bit fields, one status bit field for each subblock. The status bit fields, in addition to shared-, owner-, and valid-bits, have a pending-bit which, when set, indicates a pending uncompleted outstanding operation on a subblock, and will prevent the CPU from overwriting the corresponding subblock.

Abstract: A high speed, synchronous, packet-switched inter-chip bus apparatus and method for transferring data between multiple system buses and a cache controller. In the preferred embodiment, the bus connects a cache controller client within the external cache of a processor to a plurality of bus watcher clients, each of which is coupled to a separate system bus. The bus allows the cache controller to provide independent processor-side access to the cache and allows the bus watchers to handle functions related to bus-snooping. An arbiter is employed to allow the bus to be multiplexed between the bus watchers and cache controller. Flow control mechanisms are also employed to ensure that queues receiving packets or arbitration requests over the bus never overflow. A default grantee mechanism is employed to minimize the arbitration latency due to a request for the bus when the bus is idle.

Abstract: A single error correction, double error detection function for cache memories does not affect the normal cache access time the addition of the ECC function. Check bits are provided for multiple bytes of data, thereby lowering the overhead of the error detecting and correcting technique. When a single error is detected, a cycle is inserted by the control circuitry of the cache chip. At the same time, the clocks for the CPU are held high until released by the cache chip on the next cycle. Error correction on multi-byte data is performed using the 72/64 Hamming code. The technique requires a 2-port cache array (one write port, and one read port). However, the density of a true 2-port array is too low; therefore, the technique is implemented with a 1-port array using a time multiplexing technique, providing an effective 2-port array but with the density of a single port array.