Abstract: The present invention relates to an antigen-binding molecule comprising a heavy chain variable region comprising a heavy-chain complementarity-determining region 1 (HCDR1) comprising an amino acid sequence represented by Sequence No. 1, an HCDR2 comprising an amino acid sequence represented by Sequence No. 2, and an HCDR3 comprising an amino acid sequence represented by Sequence No. 3; a light-chain variable region comprising a light-chain complementarity-determining region 1 (LCDR1) comprising an amino acid sequence represented by Sequence No. 4, an LCDR2 comprising an amino acid sequence represented by Sequence No. 5, and an LCDR3 comprising an amino acid sequence represented by Sequence No. 6; wherein the antigen-binding molecule is a T cell receptor (TCR); and to a cell line expressing the same.

Abstract: Disclosed are novel compounds of Chemical Formula 1, optical isomers of the compounds, and pharmaceutically acceptable salts of the compounds or the optical isomers. The compounds, isomers, and salts exhibit excellent activity as GLP-1 receptor agonists. In particular, they, as GLP-1 receptor agonists, exhibit excellent glucose tolerance, thus having a great potential to be used as therapeutic agents for metabolic diseases. Moreover, they exhibit excellent pharmacological safety for cardiovascular systems.

Abstract: Disclosed are a method of processing digitalized drawing and a compute program. One aspect of the present invention provides a method of processing digitalized drawing data by a computer, the method including: providing digitalized drawing having a line ID (S10); splitting the line ID into a plurality of topologies, which are smallest units that are mutually exclusive and do not overlap each other (S20); generating a pipe system network (PSN) by recombining the plurality of topologies, wherein the plurality of topologies are recombined such that a start point and an end point of the PSN are each independently Equipment, Branch or Header (S30); and generating a path item (PI) by arranging internal objects on the digitalized drawing existing between the start point and the end point of the pipe system network (PSN) and adding necessary information usable in a subsequent process (S40).

Abstract: A non-volatile memory device and its manufacturing method are provided. The method includes the following steps. A plurality of isolation structures are formed in a substrate. A first polycrystalline silicon layer is formed in the substrate and between two adjacent isolation structures. A first implantation process is performed to implant a first dopant into the first polycrystalline silicon layer and the isolation structures. A portion of each of the isolation structures is partially removed, and the remaining portion of each of the isolation structures has a substantially flat top surface. An annealing process is performed after partially removing the isolation structures to uniformly diffuse the first dopant in the first polycrystalline silicon layer. A dielectric layer is formed on the first polycrystalline silicon layer, and a second polycrystalline silicon layer is formed on the dielectric layer.

Abstract: Provided is an integrated circuit including a substrate, a plurality of first gate structures, a protective layer, a second gate structure, a source region, and a drain region. The substrate has a cell region and a peripheral region. The plurality of first gate structures are disposed in the cell region. A top surface and a sidewall of the plurality of first gate structures are covered by the protective layer. The second gate structure is disposed in the peripheral region. The source region and the drain region are disposed on the both side of the second gate structure. A manufacturing method of the integrated circuit is also provided.

Abstract: Provided is an integrated circuit including a substrate, a plurality of first gate structures, a protective layer, a second gate structure, a source region, and a drain region. The substrate has a cell region and a peripheral region. The plurality of first gate structures are disposed in the cell region. A top surface and a sidewall of the plurality of first gate structures are covered by the protective layer. The second gate structure is disposed in the peripheral region. The source region and the drain region are disposed on the both side of the second gate structure. A manufacturing method of the integrated circuit is also provided.

Abstract: A non-volatile memory device and its manufacturing method are provided. The method includes the following steps. A plurality of isolation structures are formed in a substrate. A first polycrystalline silicon layer is formed in the substrate and between two adjacent isolation structures. A first implantation process is performed to implant a first dopant into the first polycrystalline silicon layer and the isolation structures. A portion of each of the isolation structures is partially removed, and the remaining portion of each of the isolation structures has a substantially flat top surface. An annealing process is performed after partially removing the isolation structures to uniformly diffuse the first dopant in the first polycrystalline silicon layer. A dielectric layer is formed on the first polycrystalline silicon layer, and a second polycrystalline silicon layer is formed on the dielectric layer.

Abstract: A method of manufacturing DRAM capacitor. An active region is formed above a substrate. A plurality of parallel word lines is formed above the substrate. A first plug and a second plug are formed between the word lines in locations for forming the desired bit line contact and node contact, respectively. Insulation material is deposited into the remaining space between the word lines. A bit line contact is formed above the first plug. A plurality of parallel bit lines is formed above the substrate. The bit lines are perpendicular to the word lines. The bit line is electrically connected to the substrate through the bit line contact and the first plug. The bit lines are electrically insulated from each other. Furthermore, each bit line is covered on top by a hard material layer. Finally, a node contact is formed over the second plug.

Abstract: A method of creating a DRAM capacitor structure, featuring a crown shaped storage node structure, has been developed. The crown shaped storage node structure, features the formation of an hemispherical grain, (HSG), silicon layer, only on a top portion of the structure, with the bottom portion of the crown shaped storage node structure, featuring non - HSG, or smooth surfaces. This configuration is achieved via creation of a capacitor opening, in a doped oxide - undoped oxide, composite insulator layer, used as the shape for subsequent formation of an amorphous silicon crown shaped structure. Selective removal of the overlying doped oxide layer, allows selective formation of an HSG silicon layer, only on the exposed top portion of the amorphous silicon crown shaped structure.

Abstract: A process for creating a DRAM capacitor structure, featuring a doped polysilicon layer, overlying a crown shaped storage node electrode, has been developed. The process features the use of an HSG silicon layer, on a doped amorphous silicon, storage node shape, with the HSG silicon layer supplying increased surface area, and thus increased capacitance, for the DRAM capacitor. A doped polysilicon layer, selectively deposited on the underlying HSG silicon layer, supplies additional dopant to the HSG silicon layer, residing on the doped amorphous silicon, storage node shape, thus minimizing a capacitance depletion phenomena, that can be present with lightly doped storage node structures.

Abstract: A method for insitu forming a SiN layer and an overlying Silicon oxynitride layer in one chamber. A substrate is loaded into a chamber. The substrate has thereover a polysilicon layer and a overlying metal layer. In a first in-situ step, a nitride layer is deposited using a LPCVD process over the substrate. The nitride layer is preferably formed at a temperature between 650 and 800.degree. C. and flowing SiH.sub.2 Cl.sub.2 and NH.sub.3. In a second in-situ step, an oxynitride layer is deposited over the nitride layer. The oxynitride layer acts as a bottom anti-reflective coating (BARC). The oxynitride (SiON) layer can be formed by a LPCVD process. Second, the LPCVD oxynitride can be formed a temperature between 600 and 800.degree. C. with a SiH.sub.4 flow and a N.sub.2 O flow. The substrate is removed from the chamber. A photoresist layer is formed over the oxynitride layer. The photoresist layer is exposed using the oxynitride layer as a bottom anti-reflective coating (BARC).

Abstract: A process for creating a DRAM capacitor structure, comprised of a storage node electrode, featuring an HSG silicon layer, on the surface of the storage node electrode, used to increase capacitor surface area, has been developed. The process features the use of a UHV system, allowing: a pre-clean procedure; an HSG seeding procedure; an anneal procedure used to create an HSG silicon layer; and a silicon nitride deposition; all to be performed in situ, without exposure to air, thus removing, and avoiding, unwanted native oxide layers. This invention allows a nitride--oxide, capacitor dielectric layer, to be formed in situ, in the UHV system, on an underlying storage node electrode structure, which in turn experienced in situ procedures, in the UHV system, resulting in HSG silicon layer, formed after an in situ, pre-clean, an HSG silicon seeding procedure, and an anneal procedure.

Abstract: An improved and new process for fabricating planarized isolation trenches, wherein sharp corners at the top periphery of the trench are eliminated and erosion of insulating material at the edges of isolation trenches is suppressed, has been developed. The process uses a two layer mask to etch the isolation trench, followed by an isotropic etch to recess the first layer of the mask. An oxide liner is formed in the trench and across the exposed edge of the trench resulting in rounding the corners of the trench. Then, a second isotropic etch is used to recess the edge of the second mask layer, so that its opening now is beyond the edge of the trench. An oxide layer is conformally deposited over all exposed surfaces and fills the trench. After CMP to planarize the oxide layer, the remaining oxide fills the trench and, also, extends a small distance beyond the edge of the trench and serves to protect edge of the trench during subsequent etching.

Abstract: A process for creating a storage node electrode for a DRAM capacitor structure, featuring increased surface area accomplished using an HSG silicon layer as the top layer for the storage node electrode, has been developed. The process features the use of a composite buffer layer of undoped and lightly doped amorphous silicon layers, located overlying a heavily doped amorphous silicon layer, and then followed by the deposition of HSG silicon seeds. A first anneal cycle then allows formation of an undoped HSG silicon layer to be realized on the underlying heavily doped amorphous silicon layer, via consumption of the HSG seeds, and of the composite buffer layer of undoped and lightly doped amorphous silicon layers. A second anneal cycle then allows dopant from the underlying heavily doped amorphous silicon layer to reach the undoped HSG silicon layer, resulting in a doped HSG silicon layer.

Abstract: A process for creating an insulator filled, shallow trench isolation region, in a semiconductor substrate, has been developed. The process features the use of a high temperature hydrogen anneal, performed after an anisotropic RIE procedure, used to create the shallow trench shape, in the semiconductor substrate. The high temperature hydrogen anneal procedure repairs defects in the semiconductor substrate, created by the shallow trench, RIE procedure, and also creates a denuded zone, at or near the shallow trench shape, exposed silicon surface. The defect free denuded zone allows the formation of a uniform insulator trench liner to be realized, and also allows a minimum of junction leakage to occur at the region in which a source/drain-substrate junction, is butted against the side of the insulator filled, shallow trench.

Abstract: A process for creating a crown shaped storage node electrode, covered with an HSG silicon layer, used to increase the surface area, and thus the capacitance of, high density, DRAM designs, has been developed. The process features creating a crown shaped storage node shape, from a composite amorphous silicon layer, wherein the composite amorphous silicon layer is comprised of a heavily doped amorphous silicon layer, used to alleviate capacitance depletion phenomena, sandwiched between undoped, or lightly doped, amorphous silicon layers, used to selectively accept the overlying HSG silicon layer. The process also features the use an HF vapor pre-clean procedure, followed by an in situ, selective deposition of HSG silicon seeds, in a conventional LPCVD chamber, prior to anneal cycle used to form the HSG silicon layer.

Abstract: A method for creating a stacked, or crown shaped, capacitor structure, with increased surface area, obtained using a storage node electrode, comprised of HSG silicon grains on the surface of the storage node electrode, has been developed. An in situ procedure, allows HSG silicon seeds to be selectively formed, only on the exposed surfaces of a amorphous silicon storage node electrode shape, in an LPCVD system, directly after an HF preclean step. A subsequent anneal, again performed in situ, in the LPCVD system, results in the formation of HSG silicon grains, converted from the HSG silicon seeds.

Abstract: A process creating a crown shaped storage node electrode, for high density, DRAM designs, has been developed. The process features the formation of an hemispherical grain, (HSG), silicon layer, only on the outside walls of the amorphous silicon vertical shapes, of the crown shaped storage node electrode. The HSG silicon layer is formed from HSG silicon seeds, and from undoped, or lightly doped amorphous silicon layers, or a combination of both. The amorphous silicon vertical shapes are comprised of an undoped, or lightly doped amorphous silicon layer, placed as the outside layer, while a heavily doped amorphous silicon layer is used for the inside layer.

Abstract: A method for creating a stacked capacitor structure, with increased surface area, needed for high density, DRAM designs, has been developed. A storage node electrode, featuring a top surface of HSG polysilicon lumps, is used for the surface area increase. A feature of this invention is the use of a thin, heavily doped, polysilicon layer, formed on the HSG polysilicon lumps, resulting in improved adhesion between HSG polysilicon lumps and the underlying polysilicon storage node shape. The thin, heavily doped, polysilicon layer also supplies dopant to underlying HSG polysilicon lumps, needed to reduce a capacitor depletion phenomena which can occur if undoped HSG polysilicon lumps are used.

Abstract: A method for creating stacked capacitor structures, with increased surface area, obtained using storage node electrode structures comprised of an HSG silicon layer, on a heavily doped amorphous silicon layer, both overlying polysilicon storage node shapes, has been developed. A dilute hydrofluoric acid pre-clean procedure is used prior to depositing a heavily doped amorphous silicon layer, on underlying polysilicon storage node shapes. An overlying second amorphous silicon layer is in situ deposited, in the same furnace used for the prior deposition of heavily doped amorphous silicon layer, followed by an in situ seeding/annealing procedure, converting the second amorphous silicon layer to an HSG silicon layer. This invention features the use of the acid pre-clean, to improve adhesion of the heavily doped amorphous silicon layer, to underlying polysilicon storage node shapes.