Patents by Inventor Jung-Ho Do
Jung-Ho Do has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9653394Abstract: A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line.Type: GrantFiled: February 11, 2015Date of Patent: May 16, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Vincent Chun Fai Lau, Jung-ho Do, Byung-sung Kim, Chul-hong Park
-
Publication number: 20170133367Abstract: Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a gate isolation region cutting the first gate line, the second gate line and the third gate line and extending in a second direction across the first direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact, and a second metal line electrically connected to the first gate contact.Type: ApplicationFiled: January 26, 2017Publication date: May 11, 2017Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Hoon BAEK, Sun-Young PARK, Sang-Kyu OH, Ha-Young KIM, Jung-Ho DO, Moo-Gyu BAE, Seung-Young LEE
-
Patent number: 9646960Abstract: A system-on-chip device may include a substrate with an active pattern, a gate electrode crossing the active pattern and extending in a first direction, and a first metal layer electrically connected to the active pattern and the gate electrode. The first metal layer may include a first metal line extending in the first direction and a second metal line spaced apart from the first metal line in the first direction to extend in a second direction crossing the first direction. The first and second metal lines may include first and second sidewalls parallel to the second direction, the first and second sidewalls may face each other, and the first sidewall may have a length that is two or three times a minimum line width.Type: GrantFiled: February 17, 2016Date of Patent: May 9, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Sanghoon Baek, Jung-Ho Do, Taejoong Song, Giyoung Yang, Seungyoung Lee, Jinyoung Lim
-
Patent number: 9640444Abstract: Provided is a method of fabricating a semiconductor device with a field effect transistor. The method may include forming a first gate electrode and a second gate electrode extending substantially parallel to each other and each crossing a PMOSFET region on a substrate and an NMOSFET region on the substrate; forming an interlayered insulating layer covering the first gate electrode and the second gate electrode; patterning the interlayered insulating layer to form a first sub contact hole on the first gate electrode, the first sub contact hole being positioned between the PMOSFET region and the NMOSFET region, when viewed in a plan view; and patterning the interlayered insulating layer to form a first gate contact hole and to expose a top surface of the second gate electrode, wherein the first sub contact hole and the first gate contact hole form a single communication hole.Type: GrantFiled: July 23, 2015Date of Patent: May 2, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Ho Do, Sanghoon Baek, Sang-Kyu Oh, Kwanyoung Chun, Sunyoung Park, Taejoong Song
-
Patent number: 9589955Abstract: Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a gate isolation region cutting the first gate line, the second gate line and the third gate line and extending in a second direction across the first direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact, and a second metal line electrically connected to the first gate contact.Type: GrantFiled: October 1, 2015Date of Patent: March 7, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Hoon Baek, Sun-Young Park, Sang-Kyu Oh, Ha-Young Kim, Jung-Ho Do, Moo-Gyu Bae, Seung-Young Lee
-
Publication number: 20170062475Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.Type: ApplicationFiled: September 30, 2016Publication date: March 2, 2017Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Taejoong SONG, Ha-Young KIM, Jung-Ho DO, Sanghoon BAEK, Jinyoung LIM, Kwangok JEONG
-
Publication number: 20170062403Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.Type: ApplicationFiled: August 17, 2016Publication date: March 2, 2017Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Taejoong SONG, Ha-Young KIM, Jung-Ho DO, Sanghoon BAEK, Jinyoung LIM, Kwangok JEONG
-
Publication number: 20170032074Abstract: A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.Type: ApplicationFiled: June 16, 2016Publication date: February 2, 2017Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: TAEJOONG SONG, SANGHOON BAEK, SUNGWE CHO, JUNG-HO DO, GIYOUNG YANG, JINYOUNG LIM
-
Publication number: 20160351583Abstract: An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.Type: ApplicationFiled: August 9, 2016Publication date: December 1, 2016Applicant: Samsung Electronics Co., Ltd.Inventors: Sang-hoon BAEK, Sang-kyu Oh, Jung-Ho Do, Sun-young Park, Seung-young Lee, Hyo-sig Won
-
Patent number: 9496179Abstract: A method of manufacturing a semiconductor device includes forming an active pattern and a gate electrode crossing the active pattern on a substrate, forming a first contact connected to the active pattern at a side of the gate electrode, forming a second contact connected to the gate electrode, and forming a third contact connected to the first contact at the side of the gate electrode. The third contact is formed using a photomask different from that used to form the first contact. A bottom surface of the third contact is disposed at a level in the device lower than the level of a top surface of the first contact.Type: GrantFiled: August 24, 2015Date of Patent: November 15, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Ho Do, Sanghoon Baek, Sunyoung Park, Sang-Kyu Oh, Jintae Kim, Hyosig Won
-
Publication number: 20160300826Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, an insulating layer on the gate electrode, first and second lower vias in the insulating layer, first and second lower metal lines provided on the insulating layer and respectively connected to the first and second lower vias, and first and second upper metal lines provided on and respectively connected to the first and second lower metal lines. When viewed in a plan view, the first lower via is overlapped with the second upper metal line, and the second lower via is overlapped with the first upper metal line.Type: ApplicationFiled: April 8, 2016Publication date: October 13, 2016Inventors: Seungyoung LEE, Sanghoon BAEK, Jung-Ho DO
-
Patent number: 9449970Abstract: A semiconductor device includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a third gate structure extending in the first direction and provided between the first and second gate structures, a first contact connected to the first gate structure and having a first width in the second direction, a second contact connected to the second gate structure and having a second width in the second direction, and a third contact connected to the third gate structure and having a third width in the second direction. The first, second, and third contacts may be aligned with each other in the second direction to constitute one row. The first and second widths may be greater than the third width.Type: GrantFiled: August 19, 2015Date of Patent: September 20, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Ho Do, Sanghoon Baek, Sunyoung Park, Moo-Gyu Bae, Taejoong Song
-
Publication number: 20160254256Abstract: A system-on-chip device may include a substrate with an active pattern, a gate electrode crossing the active pattern and extending in a first direction, and a first metal layer electrically connected to the active pattern and the gate electrode. The first metal layer may include a first metal line extending in the first direction and a second metal line spaced apart from the first metal line in the first direction to extend in a second direction crossing the first direction. The first and second metal lines may include first and second sidewalls parallel to the second direction, the first and second sidewalls may face each other, and the first sidewall may have a length that is two or three times a minimum line width.Type: ApplicationFiled: February 17, 2016Publication date: September 1, 2016Inventors: SANGHOON BAEK, JUNG-HO DO, TAEJOONG SONG, GIYOUNG YANG, SEUNGYOUNG LEE, JINYOUNG LIM
-
Patent number: 9431383Abstract: An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.Type: GrantFiled: July 16, 2015Date of Patent: August 30, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-hoon Baek, Sang-kyu Oh, Jung-ho Do, Sun-young Park, Seung-young Lee, Hyo-sig Won
-
Publication number: 20160099211Abstract: Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a gate isolation region cutting the first gate line, the second gate line and the third gate line and extending in a second direction across the first direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact, and a second metal line electrically connected to the first gate contact.Type: ApplicationFiled: October 1, 2015Publication date: April 7, 2016Inventors: Sang-Hoon BAEK, Sun-Young PARK, Sang-Kyu OH, Ha-Young KIM, Jung-Ho DO, Moo-Gyu BAE, Seung-Young LEE
-
Publication number: 20160085904Abstract: A semiconductor device and a layout verification method of a semiconductor device are provided. The layout verification method includes forming a plurality of standard cells each having a first type of a cross coupled structure (XC) and a second type of the XC on a substrate of the semiconductor device, forming a plurality of first inverters in which the first type of the XC is activated in the a plurality of the standard cells and a plurality of second inverters in which the second type of the XC is activated in the a plurality of the standard cells and estimating an electrical characteristic of the first type of the XC or the second type of the XC by measuring a magnitude of a signal delay of the plurality of the first inverters or the plurality of the second inverters.Type: ApplicationFiled: September 3, 2015Publication date: March 24, 2016Inventors: Taejoong SONG, Jung-Ho DO, Changho HAN
-
Publication number: 20160086947Abstract: According to example embodiments, a semiconductor device and a method for manufacturing the same are provided, the semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region, a first gate electrode and a second gate electrode on the PMOSFET region, a third gate electrode and a fourth gate electrode on the NMOSFET region, and a first contact and a second contact connected to the first gate electrode and the fourth gate electrode, respectively. The first to fourth gate cut electrodes define a gate cut region that passes between the first and third gate electrodes and between the second and fourth gate electrodes. A portion of each of the first and second contacts overlaps with the gate cut region when viewed from a plan view.Type: ApplicationFiled: September 15, 2015Publication date: March 24, 2016Inventors: Panjae PARK, Sutae KIM, Donghyun KIM, Ha-Young KIM, Jung-Ho DO, Sunyoung PARK, Sanghoon BAEK, Jaewan CHOI
-
Publication number: 20160056153Abstract: A semiconductor device includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a third gate structure extending in the first direction and provided between the first and second gate structures, a first contact connected to the first gate structure and having a first width in the second direction, a second contact connected to the second gate structure and having a second width in the second direction, and a third contact connected to the third gate structure and having a third width in the second direction. The first, second, and third contacts may be aligned with each other in the second direction to constitute one row. The first and second widths may be greater than the third width.Type: ApplicationFiled: August 19, 2015Publication date: February 25, 2016Inventors: Jung-Ho DO, SANGHOON BAEK, Sunyoung PARK, Moo-Gyu BAE, TAEJOONG SONG
-
Publication number: 20160056083Abstract: A method of manufacturing a semiconductor device includes forming an active pattern and a gate electrode crossing the active pattern on a substrate, forming a first contact connected to the active pattern at a side of the gate electrode, forming a second contact connected to the gate electrode, and forming a third contact connected to the first contact at the side of the gate electrode. The third contact is formed using a photomask different from that used to form the first contact. A bottom surface of the third contact is disposed at a level in the device lower than the level of a top surface of the first contact.Type: ApplicationFiled: August 24, 2015Publication date: February 25, 2016Inventors: JUNG-HO DO, SANGHOON BAEK, SUNYOUNG PARK, SANG-KYU OH, JINTAE KIM, HYOSIG WON
-
Publication number: 20160027769Abstract: An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.Type: ApplicationFiled: July 16, 2015Publication date: January 28, 2016Inventors: Sang-hoon BAEK, Sang-kyu OH, Jung-ho DO, Sun-young PARK, Seung-young LEE, Hyo-sig WON