Abstract: A method for increasing salicide thickness and effective polysilicon width at a narrow polysilicon line while reducing resistance and reducing source/drain bridging risk in the fabrication of a silicided polysilicon gate is described. A polysilicon layer is provided overlying a gate oxide layer on a semiconductor substrate. A dielectric layer, such as silicon oxide, is deposited overlying the polysilicon layer. The silicon oxide layer, polysilicon layer, and gate oxide layer are patterned to form a polysilicon gate electrode having a silicon oxide layer on top of the gate electrode. Dielectric spacers, such as silicon nitride, are formed on the sidewalls of the gate electrode and the silicon oxide layer. In an alternative, silicon spacers may be formed between the gate and the silicon nitride spacers to increase the effective width of the polysilicon line. Source and drain regions associated with the gate electrode are formed within the semiconductor substrate.

Abstract: This invention provides a multi-layer multi-phase phase shifting photomask and a method for fabricating the same. The photomask of this invention uses a number of phase shifting layers each layer providing less than 180°optical phase shift to provide a total optical phase shift of 180°. The multi-layer multi-phase phase shifting photomask provides a gradual transition form no phase shift to 180° phase shift at pattern edges thereby improving image quality. The patterns in the layers of phase shifting material are formed using non critical etching steps. The thickness of the phase shifting layers is controlled by the deposition of the layers of phase shifting material which is relatively easy to control.

Abstract: The outer box of a box-in-box alignment pattern can be difficult to see if implemented in damascene technology. The present invention solves this problem by forming its outline from a trench that is substantially deeper than the channel used to contain the damascene wiring. This trench is formed at the same time that first vias are etched so no extra processing steps are needed, only one extra mask. The metal used for the damascene wiring also lines the inside of the trench, resulting in a structure that is easily seen during the alignment step. These outer box trenches may be simple squares or they may be ring shaped (hollow squares). Three different embodiments of the invention are described.

Abstract: A method for increasing salicide thickness and effective polysilicon width at a narrow polysilicon line while reducing resistance and reducing source/drain bridging risk in the fabrication of a silicided polysilicon gate is described. A polysilicon layer is provided overlying a gate oxide layer on a semiconductor substrate. A dielectric layer, such as silicon oxide, is deposited overlying the polysilicon layer. The silicon oxide layer, polysilicon layer, and gate oxide layer are patterned to form a polysilicon gate electrode having a silicon oxide layer on top of the gate electrode. Dielectric spacers, such as silicon nitride, are formed on the sidewalls of the gate electrode and the silicon oxide layer. In an alternative, silicon spacers may be formed between the gate and the silicon nitride spacers to increase the effective width of the polysilicon line. Source and drain regions associated with the gate electrode are formed within the semiconductor substrate.

Abstract: A method for making metal interconnections and buried metal plug structures for multilevel interconnections on semiconductor integrated circuits was achieved. The method utilizes a single patterned photoresist layer for etching trenches in an insulating layer, while at the same time protecting the device contact areas in the contact openings from being etched, thereby reducing process complexity and manufacturing cost. After the trenches are formed, the patterned photoresist layer and the photoresist in the contact openings is removed by plasma ashing, and a metal layer is deposited and etched back or chem/mech polished to form concurrently the metal interconnections and the buried metal plug contacts. The surface of the metal interconnections is coplanar with the insulating surface, thereby allowing the process to be repeated several times to complete the necessary multilevel of metal wiring needed to wire-up the integrated circuits while maintaining a planar surface.

Abstract: This invention provides a method of forming an attenuating phase shifting rim type photomask and an attenuating phase shifting rim type photomask for use in projection type lithographic apparatus. The photomask is formed by exposing a layer of negative photoresist through a second surface of a transparent mask substrate having a patterned layer of attenuating phase shifting material formed on a first surface of the transparent mask substrate. The exposed and developed photoresist forms a pedestal with sloping sides. A layer of opaque material is vertically anisotropically deposited on the top of the pedestal and that part of the patterned layer of attenuating phase shifting material not shaded by the pedestal. The pedestal and opaque material formed on the top of the pedestal is then removed to complete the mask.