Abstract: A semiconductor device structure includes a first dielectric layer disposed over a semiconductor substrate, and a second dielectric layer disposed over the first dielectric layer. The semiconductor device structure also includes a first conductive plug disposed in the first dielectric layer. An upper portion of the first conductive plug extends into the second dielectric layer. The semiconductor device structure further includes a silicide layer disposed in the second dielectric layer and covering a top surface and sidewalls of the upper portion of the first conductive plug, and a second conductive plug disposed in the second dielectric layer and directly over the first conductive plug and the silicide layer.

Abstract: A semiconductor device structure includes a first dielectric layer disposed over a semiconductor substrate, and a second dielectric layer disposed over the first dielectric layer. The semiconductor device structure includes a first dielectric layer disposed over a semiconductor substrate, and a second dielectric layer disposed over the first dielectric layer. The semiconductor device structure also includes a first conductive plug disposed in the first dielectric layer. An upper portion of the first conductive plug extends into the second dielectric layer. The semiconductor device structure further includes a silicide layer disposed in the second dielectric layer and covering a top surface and sidewalls of the upper portion of the first conductive plug, and a second conductive plug disposed in the second dielectric layer and directly over the first conductive plug and the silicide layer.

Abstract: The present application provides a semiconductor device with an edge-protecting spacer over a bonding pad. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a dielectric liner disposed between the first spacer and the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate, wherein the dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the bonding pad and covering the first spacer and the dielectric liner, wherein the conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad.

Abstract: The present application provides a semiconductor device with an edge-protecting spacer over a bonding pad. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a dielectric liner disposed between the first spacer and the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate, wherein the dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the bonding pad and covering the first spacer and the dielectric liner, wherein the conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad.

Abstract: The present disclosure provides a semiconductor device including composite pillars, a dielectric isolation structure, a sealing layer, and air spaces. The composite pillars are disposed over a substrate. Each of the composite pillars include a conductive pillar and a dielectric cap over the conductive pillar. The dielectric isolation structure is disposed between adjacent two of the composite pillars. The dielectric isolation structure includes an air gap and a liner layer enclosing the air gap. The sealing layer is at least in contact with a top portion of the dielectric isolation structure and a top of the dielectric cap. The air spacers are formed between the sealing layer, the dielectric isolation structure and the conductive pillar.

Abstract: The present disclosure provides a semiconductor device including composite pillars, a dielectric isolation structure, a sealing layer, and air spaces. The composite pillars are disposed over a substrate. Each of the composite pillars include a conductive pillar and a dielectric cap over the conductive pillar. The dielectric isolation structure is disposed between adjacent two of the composite pillars. The dielectric isolation structure includes an air gap and a liner layer enclosing the air gap. The sealing layer is at least in contact with a top portion of the dielectric isolation structure and a top of the dielectric cap. The air spacers are formed between the sealing layer, the dielectric isolation structure and the conductive pillar.

Abstract: The present disclosure provides a method for preparing a semiconductor device with air spacer for decreasing electrical coupling. The method comprises: forming a plurality of composite pillars over a substrate, wherein the composite pillars include conductive pillars and dielectric caps over the conductive pillars; transforming a sidewall portion of the conductive pillar into a first transformed portion; removing the first transformed portion such that a width of the dielectric cap is greater than a width of a remaining portion of the conductive pillar; forming a supporting pillar between adjacent two of the plurality of composite pillars; and forming a sealing layer at least contacts a top portion of the supporting pillar and a top of the dielectric cap, and air spacers are formed between the sealing layer, the supporting pillar and the remaining portions of the conductive pillars.

Abstract: The present application discloses a method for fabricating a semiconductor device. The method for fabricating a semiconductor device includes providing a substrate, forming a pad structure above the substrate, and forming a top groove on a top surface of the pad structure.

Abstract: A semiconductor device structure includes a first dielectric layer disposed over a semiconductor substrate, and a second dielectric layer disposed over the first dielectric layer. The semiconductor device structure includes a first dielectric layer disposed over a semiconductor substrate, and a second dielectric layer disposed over the first dielectric layer. The semiconductor device structure also includes a first conductive plug disposed in the first dielectric layer. An upper portion of the first conductive plug extends into the second dielectric layer. The semiconductor device structure further includes a silicide layer disposed in the second dielectric layer and covering a top surface and sidewalls of the upper portion of the first conductive plug, and a second conductive plug disposed in the second dielectric layer and directly over the first conductive plug and the silicide layer.

Abstract: A memory device includes a semiconductor substrate having a first active region and a second active region adjacent to the first active region. The memory device also includes a first word line extending across the first active region and the second active region. The memory device further includes a first source/drain region in the first active region and a second source/drain region in the second active region disposed at opposite sides of the first word line. In addition, the memory device includes a first capacitor disposed over and electrically connected to the first source/drain region in the first active region, and a second capacitor disposed over and electrically connected to the second source/drain region in the second active region. The first capacitor and the second capacitor have different sizes.

Abstract: The present disclosure provides memory devices and methods for using shared latch elements thereof. A memory device includes a substrate, an interposer disposed over the substrate, and a logic die and stacked memory dies disposed over the interposer. In the logic die, the test generation module performs a memory test operation for the memory device. The functional elements stores functional data in latch elements during a functional mode of the memory device. The repair analysis module determines memory test/repair data based on the memory test operation. The memory test/repair data comprises memory addresses of faulty memory storage locations of the memory device that are identified during the memory test operation. The repair analysis module configures the latch elements into a scan chain, accesses the memory test/repair data during the test mode of the memory device, and repairs the memory device using the memory test/repair data.

Abstract: The present application provides a semiconductor device with an edge-protecting spacer over a bonding pad. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a dielectric liner disposed between the first spacer and the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate, wherein the dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the bonding pad and covering the first spacer and the dielectric liner, wherein the conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad.

Abstract: A memory device includes a semiconductor substrate having a first active region and a second active region adjacent to the first active region. The memory device also includes a first word line extending across the first active region and the second active region. The memory device further includes a first source/drain region in the first active region and a second source/drain region in the second active region disposed at opposite sides of the first word line. In addition, the memory device includes a first capacitor disposed over and electrically connected to the first source/drain region in the first active region, and a second capacitor disposed over and electrically connected to the second source/drain region in the second active region. The first capacitor and the second capacitor have different sizes.

Abstract: The present application discloses a method for fabricating a semiconductor device. The method for fabricating a semiconductor device includes providing a substrate, forming a pad structure above the substrate, and forming a top groove on a top surface of the pad structure.

Abstract: The present disclosure provides memory devices and methods for using shared latch elements thereof. A memory device includes a substrate, an interposer disposed over the substrate, and a logic die and stacked memory dies disposed over the interposer. In the logic die, the test generation module performs a memory test operation for the memory device. The functional elements stores functional data in latch elements during a functional mode of the memory device. The repair analysis module determines memory test/repair data based on the memory test operation. The memory test/repair data comprises memory addresses of faulty memory storage locations of the memory device that are identified during the memory test operation. The repair analysis module configures the latch elements into a scan chain, accesses the memory test/repair data during the test mode of the memory device, and repairs the memory device using the memory test/repair data.

Abstract: The present disclosure provides a method for preparing a semiconductor device with air spacer for decreasing electrical coupling. The method comprises: forming a plurality of composite pillars over a substrate, wherein the composite pillars include conductive pillars and dielectric caps over the conductive pillars; transforming a sidewall portion of the conductive pillar into a first transformed portion; removing the first transformed portion such that a width of the dielectric cap is greater than a width of a remaining portion of the conductive pillar; forming a supporting pillar between adjacent two of the plurality of composite pillars; and forming a sealing layer at least contacts a top portion of the supporting pillar and a top of the dielectric cap, and air spacers are formed between the sealing layer, the supporting pillar and the remaining portions of the conductive pillars.

Abstract: The present disclosure provides a semiconductor device and a method for preparing the semiconductor device. The method includes forming a first conductive layer over a substrate, forming a first dielectric structure over the first conductive layer, transforming a sidewall portion of the first conductive layer into a first transformed portion, removing the first transformed portion such that a width of the first dielectric structure is greater than a width of a remaining portion of the first conductive layer, and forming an inter-layer dielectric (ILD) layer covering sidewalls of the first dielectric structure such that a first air spacer is formed between the ILD layer and the remaining portion of the first conductive layer.

Abstract: The present application provides a semiconductor device with an edge-protecting spacer over a bonding pad. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a dielectric liner disposed between the first spacer and the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate, wherein the dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the bonding pad and covering the first spacer and the dielectric liner, wherein the conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a pad structure positioned above the substrate, and a top groove positioned on a top surface of the pad structure. The method for fabricating the semiconductor device includes forming a pad structure over a substrate and forming a top groove on a top surface of the pad structure.

Abstract: The present disclosure provides a semiconductor device and a method for preparing the semiconductor device. The method includes forming a first conductive layer over a substrate, forming a first dielectric structure over the first conductive layer, transforming a sidewall portion of the first conductive layer into a first transformed portion, removing the first transformed portion such that a width of the first dielectric structure is greater than a width of a remaining portion of the first conductive layer, and forming an inter-layer dielectric (ILD) layer covering sidewalls of the first dielectric structure such that a first air spacer is formed between the ILD layer and the remaining portion of the first conductive layer.