Abstract: Structures with doping free connections and methods of fabrication are provided. An exemplary structure includes a substrate; a first region of a first conductivity type formed in the substrate; an overlying layer located over the substrate; a well region of a second conductivity type formed in the overlying layer; a conductive plug laterally adjacent to the well region and extending through the overlying layer to electrically contact with the first region; and a passivation layer located between the conductive plug and the well region.

Abstract: A display device, a display driving integrated circuit (DDIC), and an operation method are provided. The display device includes a display panel, a first DDIC, and a second DDIC. The first DDIC generates a display synchronization signal, and drives a first display area of a display panel according to the display synchronization signal. The second DDIC is coupled to the first DDIC to receive the display synchronization signal. The second DDIC performs a frequency tracking operation on an internal clock signal of the second DDIC by selectively using the display synchronization signal. The second DDIC drives a second display area of the display panel according to the internal clock signal and the display synchronization signal.

Abstract: A semiconductor device includes a first transistor disposed over a substrate, a second transistor disposed over the first transistor, and a conductive trace. The first transistor includes first conductive segments, corresponding to drain and source terminals of the first transistor and extending in a first direction, on a first layer. The second transistor includes second conductive segments, corresponding to drain and source terminals of the second transistor and extending in the first direction, on a second layer above the first layer. The conductive trace extends on a third layer. The first to third layers are separated from each other in the first direction, and the third layer is interposed between the first and second layers. The first conductive segments, the second conductive segments, and the conductive trace overlap in a layout view.

Abstract: A display device, a display driving integrated circuit (DDIC), and an operation method are provided. The display device includes a display panel, a first DDIC, and a second DDIC. The first DDIC generates a display synchronization signal, and drives a first display area of a display panel according to the display synchronization signal. The second DDIC is coupled to the first DDIC to receive the display synchronization signal. The second DDIC performs a frequency tracking operation on an internal clock signal of the second DDIC by selectively using the display synchronization signal. The second DDIC drives a second display area of the display panel according to the internal clock signal and the display synchronization signal.

Abstract: A semiconductor device includes a first transistor disposed over a substrate, a second disposed over the first transistor, and a conductive trace. The first transistor includes a first active area extending on a first layer. The second transistor includes a second active area extending on a second layer above the first layer. The conductive trace extends on a third layer. The first to third layers are separated from each other in a first direction, and the third layer is interposed between the first and second layers. The first active area, the second active area, and the conductive trace overlap in a layout view.

Abstract: A deep neural network (DNN) processing device with a decompressing module, comprises a storage module, for storing a plurality of binary codes, a coding tree, a zero-point value and a scale; a decompressing module, coupled to the storage module, for generating a quantized weight array according to the plurality of binary codes, the coding tree and the zero-point value wherein the quantized weight array is generated according to an aligned quantized weight array and the zero-point value; and a DNN processing module, coupled to the decompressing module, for processing an input signal according to the quantized weight array and the scale.

Abstract: A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed next to the at least one memory cell. The at least one logic cell includes fins. The fins are separated into fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups.

Abstract: A method includes: abutting a first logic cell having a first cell height to a first memory cell having the first cell height; forming a first conductive rail and a second conductive rail at opposite sides of the first memory cell, respectively; forming a plurality of first conductive rails between the first conductive rail and the second conductive rail; forming a third conductive rail and a fourth conductive rail at opposite sides of the first logic cell, respectively; and forming a plurality of second conductive rails between the third conductive rail and the fourth conductive rail. An amount of the plurality of second conductive rails is larger than an amount of the plurality of first conductive rails.

Abstract: A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed next to the at least one memory cell and includes a plurality of fins. The plurality of fins are separated into a plurality of fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups. A method is also disclosed herein.

Abstract: A semiconductor device includes: a first multi-gate field effect transistor (FET) disposed over a substrate, the first multi-gate FET including a first active region; and a second multi-gate FET disposed over the first multi-gate FET, the second multi-gate FET including a second active region. The first active region and the second active region are not fully projected in a vertical direction perpendicular to the substrate.

Abstract: A semiconductor device includes: a first multi-gate field effect transistor (FET) disposed over a substrate, the first multi-gate FET including a first active region; and a second multi-gate FET disposed over the first multi-gate FET, the second multi-gate FET including a second active region. The first active region and the second active region are not fully projected in a vertical direction perpendicular to the substrate.

Abstract: A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed next to the at least one memory cell and includes a plurality of fins. The plurality of fins are separated into a plurality of fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups. A method is also disclosed herein.

Abstract: The present disclosure relates to an optical module, including: a carrier, a emitter, a detector and an encapsulant. The carrier has a first surface. The emitter is disposed above the first surface. The detector is disposed above the first surface. The encapsulant is disposed on the first surface and exposes at least a portion of the emitter.

Abstract: A sense amplifier (SA) includes a semiconductor substrate having a source/drain (S/D) diffusion region; a pair of SA sensing devices both disposed in the S/D diffusion region; an SA enabling device disposed in the same S/D diffusion region as where the pair of SA sensing devices are disposed in; and a sense amplifier enabling signal (SAE) line for carrying an SAE signal, for turning on the SA enabling device to discharge one of the pair of SA sensing devices during a data read from the sense amplifier, wherein the SA enabling device is arranged to provide buffer protection for source/drain terminals of the pair of SA sensing devices.

Abstract: A new approach is proposed to support grouping and storing a data stream based on the types of data items in the stream for efficient data batch processing and analysis. First, the data stream is uploaded to a cloud storage, wherein the stream of data includes a plurality of data items of different types generated by and collected from different users and/or devices. The data items are then retrieved, grouped and saved by a preprocessing unit into a plurality of batch data queues, wherein data items in each batch data queue are of the same type. One or more batch processing units are then configured to fetch and batch process data items from the batch data queues and store these data items of the same data type to one or more cloud storage files for further processing and analysis on the cloud storage one batch data queue at a time.

Abstract: A wind power generation device includes a wind blocking structure, which is in a box-shaped structure fixed on ground by a bottom plane thereof; a wind vane rotating body including a rotating shaft and vanes fixed on the rotating shaft and arranged at equal angle intervals, wherein the rotating shaft is mounted on two bearings of the wind blocking structure, and the vanes are rotatable inside the box-shaped structure; a power generator connected to the rotating shaft and fixed on the box-shaped structure by a linking plate. When wind blows to the wind blocking structure to rotate the wind vane rotating body, the power generator is driven by the rotating shaft to generate electrical power. The wind power generation device can include at least two wind vane rotating bodies, or area enlarging structures added on the vanes, to increase windward areas of the vanes.

Abstract: A semiconductor device includes: a first multi-gate field effect transistor (FET) disposed over a substrate, the first multi-gate FET including a first active region; and a second multi-gate FET disposed over the first multi-gate FET, the second multi-gate FET including a second active region. The first active region and the second active region are not fully projected in a vertical direction perpendicular to the substrate.

Abstract: A display apparatus and an operation method for a display panel thereof are provided. The display apparatus includes a display panel and a voltage supply circuit. The display panel includes a pixel circuit and a common voltage line. The pixel circuit includes an organic light emitting diode (OLED), wherein a cathode of the OLED is coupled to the common voltage line. The voltage supply circuit is coupled to the common voltage line of the display panel. The voltage supply circuit supplies a common voltage to the common voltage line during a normal operation period. The voltage supply circuit supplies a reverse bias voltage higher than the common voltage to the common voltage line during a recovery period to reversely bias the OLED.

Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.

Abstract: A computing appliance for geometric planimetry is provided, comprising a container, a vertical dividing rule, a horizontal dividing rule, a horizontal point line and a middle point line. A fluid is filled into the container, and the vertical dividing rule, the horizontal dividing rule, the horizontal point line and the middle point line are configured on a same instructing surface of the container and arranged on each of the periphery surrounding like a rectangle. When the container is vertically disposed, a fluid level is aligned with the horizontal point line. And, when the container is tilted to form at least one angle, an area of at least one geometric shape can be derived by employing the vertical dividing rule, the horizontal dividing rule, the horizontal point line and the middle point line.