Abstract: A first layer is located over a substrate. The first layer includes a first dielectric component and a first conductive component. A first etching stop layer is located over the first dielectric component. A metal capping layer is located over the first conductive component. A second etching stop layer is located over the first etching stop layer and over the metal capping layer. A second layer is located over the second etching stop layer. The second layer includes a second dielectric component and a second conductive component. A third conductive component electrically interconnects the second conductive component to the first conductive component.

Abstract: A plurality of high-k metal gate (HKMG) structures is formed over a substrate. The (HKMG) structures are separated by a plurality of gaps. The HKMG structures each include a first dielectric layer at an upper surface of the HKMG structure. The gaps are filled with a first conductive material. A portion of the first conductive material is removed in each of the gaps through an etching-back process. A metal oxide layer is formed using a spin-on deposition process. The metal oxide layer is formed over the (HKMG) structures and over the first conductive material. A second dielectric layer is formed over the metal oxide layer. An opening is etched in the second dielectric layer. The opening is etched through the second dielectric layer and through the metal oxide layer. The opening is filled with a second conductive material.

Abstract: A first layer is located over a substrate. The first layer includes a first dielectric component and a first conductive component. A first etching stop layer is located over the first dielectric component. A metal capping layer is located over the first conductive component. A second etching stop layer is located over the first etching stop layer and over the metal capping layer. A second layer is located over the second etching stop layer. The second layer includes a second dielectric component and a second conductive component. A third conductive component electrically interconnects the second conductive component to the first conductive component.

Abstract: A first layer is located over a substrate. The first layer includes a first dielectric component and a first conductive component. A first etching stop layer is located over the first dielectric component. A metal capping layer is located over the first conductive component. A second etching stop layer is located over the first etching stop layer and over the metal capping layer. A second layer is located over the second etching stop layer. The second layer includes a second dielectric component and a second conductive component. A third conductive component electrically interconnects the second conductive component to the first conductive component.

Abstract: A plurality of high-k metal gate (HKMG) structures is formed over a substrate. The (HKMG) structures are separated by a plurality of gaps. The HKMG structures each include a first dielectric layer at an upper surface of the HKMG structure. The gaps are filled with a first conductive material. A portion of the first conductive material is removed in each of the gaps through an etching-back process. A metal oxide layer is formed using a spin-on deposition process. The metal oxide layer is formed over the (HKMG) structures and over the first conductive material. A second dielectric layer is formed over the metal oxide layer. An opening is etched in the second dielectric layer. The opening is etched through the second dielectric layer and through the metal oxide layer. The opening is filled with a second conductive material.

Abstract: A plurality of high-k metal gate (HKMG) structures is formed over a substrate. The (HKMG) structures are separated by a plurality of gaps. The HKMG structures each include a first dielectric layer at an upper surface of the HKMG structure. The gaps are filled with a first conductive material. A portion of the first conductive material is removed in each of the gaps through an etching-back process. A metal oxide layer is formed using a spin-on deposition process. The metal oxide layer is formed over the (HKMG) structures and over the first conductive material. A second dielectric layer is formed over the metal oxide layer. An opening is etched in the second dielectric layer. The opening is etched through the second dielectric layer and through the metal oxide layer. The opening is filled with a second conductive material.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate and the first conductive structure. The semiconductor device structure includes a second conductive structure over the first conductive structure and extending into the first dielectric layer. The second conductive structure is electrically connected to the first conductive structure. The semiconductor device structure includes a cover layer between the second conductive structure and the first dielectric layer. The cover layer surrounds the second conductive structure, the second conductive structure passes through the cover layer and is partially between the cover layer and the first conductive structure, and the cover layer includes a metal oxide.

Abstract: A first layer is located over a substrate. The first layer includes a first dielectric component and a first conductive component. A first etching stop layer is located over the first dielectric component. A metal capping layer is located over the first conductive component. A second etching stop layer is located over the first etching stop layer and over the metal capping layer. A second layer is located over the second etching stop layer. The second layer includes a second dielectric component and a second conductive component. A third conductive component electrically interconnects the second conductive component to the first conductive component.

Abstract: A first conductive element is disposed in a first dielectric layer. An etching stop layer is disposed on the first dielectric layer but not on the first conductive element. A first metal capping layer segment is disposed on the first conductive element but not on the first dielectric layer. The etching stop layer has a greater thickness than the first metal capping layer segment. A first segment of a second conductive element is disposed on the first metal capping layer segment. A second segment of the second conductive element is disposed over the first segment of the second conductive element and partially over the etching stop layer. A third conductive element is disposed over the second conductive element.

Abstract: The present disclosure provides a method that includes providing a substrate having a first dielectric material layer and first conductive features that are laterally separated from each other by segments of the first dielectric material layer; depositing a first etch stop layer on the first dielectric material layer and the first conductive features, thereby forming the first etch stop layer having oxygen-rich portions self-aligned with the segments of the first dielectric material layer and oxygen-poor portions self-aligned with the first conductive features; performing a selective removal process to selectively remove the oxygen-poor portions of the first etch stop layer; forming a second etch stop layer on the first conductive features and the oxygen-rich portions of the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; and forming a conductive structure in the second dielectric material layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate and the first conductive structure. The semiconductor device structure includes a second conductive structure over the first conductive structure and extending into the first dielectric layer. The second conductive structure is electrically connected to the first conductive structure. The semiconductor device structure includes a cover layer between the second conductive structure and the first dielectric layer. The cover layer surrounds the second conductive structure, the second conductive structure passes through the cover layer and is partially between the cover layer and the first conductive structure, and the cover layer includes a metal oxide.

Abstract: The present disclosure provides a method that includes providing a substrate having a first dielectric material layer and first conductive features that are laterally separated from each other by segments of the first dielectric material layer; depositing a first etch stop layer on the first dielectric material layer and the first conductive features, thereby forming the first etch stop layer having oxygen-rich portions self-aligned with the segments of the first dielectric material layer and oxygen-poor portions self-aligned with the first conductive features; performing a selective removal process to selectively remove the oxygen-poor portions of the first etch stop layer; forming a second etch stop layer on the first conductive features and the oxygen-rich portions of the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; and forming a conductive structure in the second dielectric material layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate. The first dielectric layer has a first opening exposing the first conductive structure. The semiconductor device structure includes a cover layer covering a first inner wall of the first opening. The cover layer has a second opening exposing the first conductive structure. The cover layer includes a metal oxide. The semiconductor device structure includes a second conductive structure filled in the first opening and surrounded by the cover layer. The second conductive structure is electrically connected to the first conductive structure.

Abstract: A first conductive element is disposed. in a first dielectric layer. An etching stop layer is disposed on the first dielectric layer but not on the first conductive element. A first metal capping layer segment is disposed on the first conductive element but not on the first dielectric layer. The etching stop layer has a greater thickness than the first metal capping layer segment. A first segment of a second conductive element is disposed on the first metal capping layer segment. A second segment of the second conductive element is disposed over the first segment of the second conductive element and partially over the etching stop layer. A third conductive element is disposed over the second conductive element.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate. The first dielectric layer has a first opening exposing the first conductive structure. The semiconductor device structure includes a cover layer covering a first inner wall of the first opening. The cover layer has a second opening exposing the first conductive structure. The cover layer includes a metal oxide. The semiconductor device structure includes a second conductive structure filled in the first opening and surrounded by the cover layer. The second conductive structure is electrically connected to the first conductive structure.

Abstract: A layer of an interconnect structure is formed over a substrate. The layer contains an interlayer dielectric (ILD) material and a metal line disposed in the ILD. A first etching stop layer is formed on the ILD but not on the metal line. The first etching stop layer is formed through a selective atomic layer deposition (ALD) process. A second etching stop layer is formed over the first etching stop layer. A high etching selectivity exists between the first and second etching stop layers. A via is formed to be at least partially aligned with, and electrically coupled to, the metal line. The first etching stop layer prevents the ILD from being etched through during the formation of the via.

Abstract: The present disclosure provides a method that includes providing a substrate having a first dielectric material layer and first conductive features that are laterally separated from each other by segments of the first dielectric material layer; depositing a first etch stop layer on the first dielectric material layer and the first conductive features, thereby forming the first etch stop layer having oxygen-rich portions self-aligned with the segments of the first dielectric material layer and oxygen-poor portions self-aligned with the first conductive features; performing a selective removal process to selectively remove the oxygen-poor portions of the first etch stop layer; forming a second etch stop layer on the first conductive features and the oxygen-rich portions of the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; and forming a conductive structure in the second dielectric material layer.

Abstract: A layer of an interconnect structure is formed over a substrate. The layer contains an interlayer dielectric (ILD) material and a metal line disposed in the ILD. A first etching stop layer is formed on the ILD but not on the metal line. The first etching stop layer is formed through a selective atomic layer deposition (ALD) process. A second etching stop layer is formed over the first etching stop layer. A high etching selectivity exists between the first and second etching stop layers. A via is formed to be at least partially aligned with, and electrically coupled to, the metal line. The first etching stop layer prevents the ILD from being etched through during the formation of the via.

Abstract: A plurality of high-k metal gate (HKMG) structures is formed over a substrate. The (HKMG) structures are separated by a plurality of gaps. The HKMG structures each include a first dielectric layer at an upper surface of the HKMG structure. The gaps are filled with a first conductive material. A portion of the first conductive material is removed in each of the gaps through an etching-back process. A metal oxide layer is formed using a spin-on deposition process. The metal oxide layer is formed over the (HKMG) structures and over the first conductive material. A second dielectric layer is formed over the metal oxide layer. An opening is etched in the second dielectric layer. The opening is etched through the second dielectric layer and through the metal oxide layer. The opening is filled with a second conductive material.