Abstract: A capacitor device and a manufacturing method thereof are disclosed in the present invention. The capacitor device includes pad structures, bottom electrodes, a top electrode, and a dielectric layer. The bottom electrodes are disposed on the pad structures, respectively. The top electrode is disposed on the bottom electrodes. The dielectric layer is disposed between the top electrode and the bottom electrodes. The top electrode includes at least one void. The manufacturing throughput of the manufacturing method of the memory device may be enhanced accordingly.

Abstract: A semiconductor structure includes a base in which a first doped region is provided and an active pillar group arranged in the first doped region. The active pillar group includes four active pillars arranged in an array. At least one of the active pillars is provided with a notch, which faces at least one of a row centerline or a column centerline of the active pillar group.

Abstract: A purge load port which is a load port devised with a purging plate and a purging module. The purging plate has inlet nozzles, outlet nozzles and recognizer; and the purging module has an inlet opening, an outlet opening, at least a temperature and humidity sensor, at least a flow meter and at least a pressure sensor. It makes the load port incapable of purging to provide the purging techniques after being devised with purging plate and purging modules, which solves the problem of controlling the cleanness by conventional load port, and thus effectively improves the yield of wafers in microchip fabrication.

Abstract: A substrate is provided. A pillar protruding out of a surface of the substrate is already formed on the substrate, and a patterned layer is already formed on the pillar. The pillar includes a lower part, a channel region, and an upper part from bottom to top, and the lower part has a first doped region. A gate dielectric layer is formed on a sidewall at one side of the pillar. A surrounding gate is formed on the gate dielectric layer located on the channel region, and a base line electrically connected to the channel region is formed on a sidewall at the other side of the pillar. A second doped region is formed in the upper part of the pillar.

Abstract: A substrate is provided. A pillar protruding out of a surface of the substrate is already formed on the substrate, and a patterned layer is already formed on the pillar. The pillar includes a lower part, a channel region, and an upper part from bottom to top, and the lower part has a first doped region. A gate dielectric layer is formed on a sidewall at one side of the pillar. A surrounding gate is formed on the gate dielectric layer located on the channel region, and a base line electrically connected to the channel region is formed on a sidewall at the other side of the pillar. A second doped region is formed in the upper part of the pillar.

Abstract: A vertical transistor includes a substrate, a semiconductor structure, a gate, a gate dielectric layer, and a conductive layer. The semiconductor structure is disposed on the substrate and includes two vertical plates and a bottom plate. The bottom plate has an upper surface connected to bottoms of the two vertical plates and a bottom surface connected to the substrate. The gate surrounds the semiconductor structure to fill between the two vertical plates, and the gate is disposed around the two vertical plates. The gate dielectric layer is sandwiched in between the gate and the semiconductor structure, and the conductive layer is disposed on the semiconductor structure and electrically connected with tops of the two vertical plates.

Abstract: A vertical transistor including a substrate, a gate, a base line and a gate dielectric layer is provided. The substrate includes a pillar protruding out of a surface of the substrate. The pillar includes a first doped region, a channel region and a second doped region from bottom to top. The gate is disposed on a sidewall at one side of the channel region. The base line is disposed on a sidewall at the other side of the channel region and not contacted with the gate. The gate dielectric layer is disposed between the gate and the channel region.

Abstract: A vertical transistor including a substrate, a gate, a base line and a gate dielectric layer is provided. The substrate includes a pillar protruding out of a surface of the substrate. The pillar includes a first doped region, a channel region and a second doped region from bottom to top. The gate is disposed on a sidewall at one side of the channel region. The base line is disposed on a sidewall at the other side of the channel region and not contacted with the gate. The gate dielectric layer is disposed between the gate and the channel region.

Abstract: A vertical transistor includes a substrate, a semiconductor structure, a gate, a gate dielectric layer, and a conductive layer. The semiconductor structure is disposed on the substrate and includes two vertical plates and a bottom plate. The bottom plate has an upper surface connected to bottoms of the two vertical plates and a bottom surface connected to the substrate. The gate surrounds the semiconductor structure to fill between the two vertical plates, and the gate is disposed around the two vertical plates. The gate dielectric layer is sandwiched in between the gate and the semiconductor structure, and the conductive layer is disposed on the semiconductor structure and electrically connected with tops of the two vertical plates.

Abstract: An IA switch including a base seat, circuit board and panel. The base seat is connected to a connector, holes are disposed at the backside of the connector. The circuit board is integrated with a plug, chip, relay and lamp-attached button switch. The circuit board is combined with said panel at a backside. The plug is combined with said panel at a backside. The plug is combined with the connector at a front side. The panel has holes corresponding to the lamp-attached button switches. Front ends of the button switches are projected out of the holes. The panel is combined with the outside of the base seat. A picture and plastic film are stuck on the outside of the panel one after another.

Abstract: An IA switch including a base seat, circuit board and panel. The base seat is connected to a connector, holes are disposed at the backside of the connector. The circuit board is integrated with a plug, chip, relay and lamp-attached button switch. The circuit board is combined with said panel at a backside. The plug is combined with said panel at a backside. The plug is combined with the connector at a front side. The panel has holes corresponding to the lamp-attached button switches. Front ends of the button switches are projected out of the holes. The panel is combined with the outside of the base seat. A picture and plastic film are stuck on the outside of the panel one after another.

Abstract: A paper clip is formed by means of bending a metal wire to form at least three overlapped clipping portions, each clipping portion and an adjacent clipping portion defining a clipping space therebetween. Each clipping portion has a first end and a second end. The second ends of the three clipping portions are superimposed one another along a vertical plane or a horizontal plane. The first ends of the clipping portions overlap with each other with a portion of the first end of a lower clipping portion offsetting from the first end of an upper clipping portion.

Abstract: A water-saving device for a toilet comprises a tank, a tank lid mounted on top of the tank, a sink formed on the sink and communicated with a chamber in the tank via a hole in the sink, and an output tube having a lower end communicated with an inlet tube and an upper end for supplying water into the sink. A guide tube is mounted in the tank and comprises an upper end communicated with the hole of the sink and a lower end immersed in the water in the chamber of the tank such that drainage of water in the sink via the hole of the sink and the guide tube into the chamber of the tank is almost silent.