Abstract: A noise control device for a steel door includes a buffer, a shock-absorbing member, a stopping member, or only includes a colliding member. The noise control device is installed at any location of a steel door and a casting where noise may be generated when the steel door is closed or opened. The buffer consists of a cylinder, a lower sponge, a coil spring, a rod, and an upper sponge and possibly a colliding member. The buffer can be mainly installed on a deadbolt groove of the casing. The shock-absorbing member may be fixed on the steel door or the casing for reducing sound. The stopping member is fixed on the steel door to face the outer end of the buffer. The noise control device can reduce noise generated in opening and closing as much as possible and preventing the both from disfiguring or denting.

Abstract: A noise control device for a steel door includes a buffer, a shock-absorbing member, a stopping member, or only includes a colliding member. The noise control device is installed at any location of a steel door and a casting where noise may be generated when the steel door is closed or opened. The buffer consists of a cylinder, a lower sponge, a coil spring, a rod, and an upper sponge and possibly a colliding member. The buffer can be mainly installed on a deadbolt groove of the casing. The shock-absorbing member may be fixed on the steel door or the casing for reducing sound. The stopping member is fixed on the steel door to face the outer end of the buffer. The noise control device can reduce noise generated in opening and closing as much as possible and preventing the both from disfiguring or denting.

Abstract: A nasal respirator including a nasal shade body formed of a flexible sheet. The nasal shade body includes two cover sections on two opposite sides of the nasal shade body, a loose section connected between the two cover sections and two ear string members disposed on two sides of the cover sections. The loose section is composed of an outer facial layer and an inner facial layer which together define an envelope. A filter material is implanted in the envelope for achieving a filtering effect. Multiple rigid sockets are disposed in a predetermined position of the cover sections and/or the loose section for selectively connecting the nasal shade body with a mouth shade body. When the ear string members are positioned in a specific position of the ears of a wearer, the cover sections and the loose section respectively cover the chins and nose of the wearer.

Abstract: Antireflective layers (54, 86, and 109) have been developed that have discrete portions (541, 542, 861, 862, 863, 1091, and 1092). The discrete portions (541, 542, 861, 862, 863, 1091, and 1092) allow the antireflective layers (54, 86, and 109) to be used in many instances where using a single layer of uniform composition would be difficult or impossible. Alternatively, a single antireflective layer with a continuously graded composition can be used.

Abstract: An uninterrupted power supply system including a square wave oscillator, a square wave drive, a negative wave drive, a first bridge drive, a second bridge drive, a bridge circuit, a R/C low pass filter, an overload protection circuit, a high-voltage generator, and a full-wave rectifier, wherein the bridge circuit consists of pairs of oxide metal field effect transistors (insulated-gate semiconductors) respectively connected by bridging for the conversion of DC power supply into AC power supply; the high-voltage generator and the bridge circuit are mounted on an expansion card so that the output power of the system can be expanded by installing additional expansion cards.

Abstract: A method for forming a tapered opening in a silicon substrate uses NF.sub.3 and HBr. The NF.sub.3 /HBr plasma etch allows both a good taper profile, 85.degree. to 60.degree., as well as a good etch rate, approximately 2500 to 3000 .ANG./minute. Although not limited to a particular trench size, the present method is well suited for forming openings smaller than 0.45 .mu.m.

Abstract: A process for the fabrication of a non-silicided region in an integrated circuit includes the fabrication of a silicide blocking layer (24, 46, 54, 92, 112). In one embodiment, a field transistor (80) is formed by depositing a silicide blocking layer (84) overlying a field gate electrode (70) and source and drain regions (76, 78). A carbonaceous mask (86) is formed on the silicide blocking layer (84) overlying the field transistor (80). A partial etching process is performed to remove a portion of the silicide blocking layer (84) exposed by the carbonaceous mask (86). Then, the carbonaceous mask (86) is removed and the etching process is continued to completely remove portions of the silicide blocking layer (84) not originally protected by the carbonaceous mask (86). The etching process forms a silicide blocking layer (92) overlying the field transistor (80) and sidewall (94) adjacent to an MOS gate electrode (68).

Abstract: A contact is formed in a semiconductor device (10), independent of underlying topography or pitch. In one method of the present invention, an insulating layer (18) is deposited over a semiconductor substrate (12). An etch stop layer (20) is deposited over the insulating layer. A frame structure (22) is formed on the etch stop material and defines at least one contact region (23 and/or 25) within which the etch stop material is exposed. The exposed portions of the etch stop material are removed from the contact region to expose a portion of the insulating layer. The exposed portion of the insulating layer is then anisotropically etched and at least one contact (30 and/or 32) is formed in the contact region. Depending on where the contact region is positioned, either a self-aligned contact or a non-self-aligned contact may be formed, or both types of contacts may be formed simultaneously.

Abstract: A contact is formed in a semiconductor device (10), independent of underlying topography or pitch. In one method of the present invention, an insulating layer (18) is deposited over a semiconductor substrate (12). An etch stop layer (20) is deposited over the insulating layer. A frame structure (22) is formed on the etch stop material and defines at least one contact region (23 and/or 25) within which the etch stop material is exposed. The exposed portions of the etch stop material are removed from the contact region to expose a portion of the insulating layer. The exposed portion of the insulating layer is then anisotropically etched and at least one contact (30 and/or 32) is formed in the contact region. Depending on where the contact region is positioned, either a self-aligned contact or a non-self-aligned contact may be formed, or both types of contacts may be formed simultaneously.

Abstract: A semiconductor device and process wherein an ITLDD device (60) is formed having an inverse-T (IT) transistor gate with a variable work function (.PHI.) across the gate. The variable work function is attained by depositing a work function adjusting layer onto the thin gate extensions of the IT-gate. In accordance with one embodiment of the invention, a semiconductor substrate (10) of a first conductivity type is provided having a gate dielectric layer (12) formed thereon. First and second lightly doped regions (36, 37) of a second conductivity type are formed in the substrate which are spaced apart by a channel region (38). An IT-gate electrode (48) is formed on the gate dielectric layer overlying the first and second lightly doped regions and the channel region. The IT-gate has a relatively thick central section (32) and relatively thin lateral extensions (50) projecting from the central portion along the gate dielectric layer.

Abstract: A semiconductor device and process wherein an ITLDD device (60) is formed having an inverse-T (IT) transistor gate with a variable work function (.PHI.) across the gate. The variable work function is attained by depositing a work function adjusting layer onto the thin gate extensions of the IT-gate. In accordance with one embodiment of the invention, a semiconductor substrate (10) of a first conductivity type is provided having a gate dielectric layer (12) formed thereon. First and second lightly doped regions (36, 37) of a second conductivity type are formed in the substrate which are spaced apart by a channel region (38). An IT-gate electrode (48) is formed on the gate dielectric layer overlying the first and second lightly doped regions and the channel region. The IT-gate has a relatively thick central section (32) and relatively thin lateral extensions (50) projecting from the central portion along the gate dielectric layer.