Abstract: A preliminary tunnel insulation pattern and a preliminary charge storage pattern are formed on each active pattern extending in a direction, and a trench is defined between structures including the active pattern, the preliminary tunnel insulation pattern and the preliminary charge storage pattern. A preliminary isolation pattern partially fills the trench. A dielectric layer and a control gate electrode layer are formed on the preliminary charge storage pattern and the preliminary isolation pattern. The control gate electrode layer, the dielectric layer, the preliminary charge storage pattern and the preliminary tunnel insulation pattern are patterned to form gate structures including a tunnel insulation pattern, a charge storage pattern, a dielectric layer pattern and a control gate electrode. The preliminary isolation pattern is isotropically etched to form an isolation pattern and a first air gap. An insulating interlayer is formed between the gate structures to keep the first air gap.

Abstract: A preliminary tunnel insulation pattern and a preliminary charge storage pattern are formed on each active pattern extending in a direction, and a trench is defined between structures including the active pattern, the preliminary tunnel insulation pattern and the preliminary charge storage pattern. A preliminary isolation pattern partially fills the trench. A dielectric layer and a control gate electrode layer are formed on the preliminary charge storage pattern and the preliminary isolation pattern. The control gate electrode layer, the dielectric layer, the preliminary charge storage pattern and the preliminary tunnel insulation pattern are patterned to form gate structures including a tunnel insulation pattern, a charge storage pattern, a dielectric layer pattern and a control gate electrode. The preliminary isolation pattern is isotropically etched to form an isolation pattern and a first air gap. An insulating interlayer is formed between the gate structures to keep the first air gap.

Abstract: An electrophoretic display device includes an array substrate, an opposing substrate, and an electrophoretic layer disposed between the array substrate and the opposing substrate. The array substrate includes a first base substrate having a plurality of pixel regions, and a pixel electrode having a plurality of electrode patterns disposed in each of the pixel regions. The opposing substrate includes a second base substrate positioned opposite to the first base substrate, and a common electrode disposed on a surface of the second base substrate that faces the first base substrate. The electrophoretic layer includes a plurality of polarity particles dispersed in a non-polar solvent. The common electrode includes a plurality of openings disposed in a region corresponding to each of the electrode patterns.

Abstract: An electrophoretic display device includes an array substrate, an opposing substrate, and an electrophoretic layer disposed between the array substrate and the opposing substrate. The array substrate includes a first base substrate having a plurality of pixel regions, and a pixel electrode having a plurality of electrode patterns disposed in each of the pixel regions. The opposing substrate includes a second base substrate positioned opposite to the first base substrate, and a common electrode disposed on a surface of the second base substrate that faces the first base substrate. The electrophoretic layer includes a plurality of polarity particles dispersed in a non-polar solvent. The common electrode includes a plurality of openings disposed in a region corresponding to each of the electrode patterns.