Abstract: A non-volatile memory chip comprises a cell region that includes a first surface, a second surface opposite to the first surface, a first cell structure, and a second cell structure spaced apart from the first cell structure; a peripheral circuit region on the first surface of the cell region, and that includes a first peripheral circuit connected to the first cell structure, a second peripheral circuit connected to the second cell structure, and a connection circuit between the first and second peripheral circuits; a through via between the first and second cell structures and that extends from the second surface of the cell region to the connection circuit of the peripheral circuit region; a redistribution layer that covers the through via on the second surface of the cell region, is connected to the through via, and extends along the second surface; and a chip pad connected to the redistribution layer.

Abstract: The embodiments relate to a radar control device and method. Specifically, a radar control device according to the embodiments may include a transceiver configured to transmit a transmission signal to the surroundings of a host vehicle and receive a reception signal received by reflecting the transmission signal on an object, a determiner configured to generate a first range-Doppler map by performing fast Fourier transform (FFT) on the reception signal and generate a second range-Doppler map based on a comparison group including a plurality of preset temporary lateral distances, and determine a correlation coefficient between the first range-Doppler map and the second range-Doppler map, and an estimator configured to estimate a lateral distance between the host vehicle and the object based on the correlation coefficient.

Abstract: A battery capacity prediction apparatus according to an example embodiment disclosed herein includes an extraction unit configured to extract comparison data obtained by comparing a measured capacity of a battery with a reference capacity of the battery and extract capacity change data obtained by measuring a capacity change of the battery with respect to a cycle change of the battery and a controller configured to predict a capacity of the battery based on the comparison data and the capacity change data.

Abstract: A data receiving device may include a dummy stage block. The dummy stage block may include m dummy stages, wherein m is a natural number greater than or equal to two. Each of the m dummy stages may be configured to remove inter-symbol interference (ISI) from a dummy input signal using dummy coefficient information to generate a dummy output signal free of the ISI. Each of the m dummy stages may be further configured to output the dummy output signal. A normal stage block may include n normal stages, wherein n is a natural number greater than or equal to two. Each of the n normal stages may be configured to remove ISI from an input signal using coefficient information to generate an output signal free of the ISI and may be further configured to output the output signal.

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

Abstract: A method of displaying an application is provided. The method includes displaying an execution screen of a first application on a first area when the first application is executed, displaying the execution screen of the first application on a second area instead of on the first area when a second application is executed while the first application is executed, and displaying an execution screen of a second application on the first area.

Abstract: A method of displaying an application is provided. The method includes displaying an execution screen of a first application on a first area when the first application is executed, displaying the execution screen of the first application on a second area instead of on the first area when a second application is executed while the first application is executed, and displaying an execution screen of a second application on the first area.

Abstract: A method includes measuring a linearity of a first pull-up circuit, a second pull-up circuit, a third pull-up circuit, a first pull-down circuit, a second pull-down circuit and a third pull-down circuit using an initial pull-up code and an initial pull-down code, each of the first pull-up circuit, the second pull-up circuit and the third pull-up circuit having a respective resistance value determined based on a respective pull-up code, and each of the first pull-down circuit, the second pull-down circuit and the third pull-down circuit having a respective resistance value determined based on a respective pull-down code, and determining a calibration setting indicator based on the measurement result, the calibration setting indicator indicating a calibration method of a transmission driver including the first pull-up circuit, the second pull-up circuit, the third pull-up circuit, the first pull-down circuit, the second pull-down circuit and the third pull-down circuit.

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

Abstract: The present embodiments relate to a phase error compensation device and method of a radar and a radar device including the same. A phase error compensation device according to an embodiment may include a first determiner configured to determine, for each first distance to a moving target, a first phase error between a phase of a first reception signal corresponding to a first transmission signal transmitted from a first transmission antenna and a phase of a second reception signal corresponding to a second transmission signal from a second transmission antenna, and a lookup table generator configured to generate and store a lookup table for phase compensation including phase compensation values for each distance based on the first phase error for each first distance.

Abstract: A memory device, a host device and a method of operating the memory device are provided. The memory device includes a data signal generator configured to provide a data signal to a transmission driver, the transmission driver configured to output a multi-level signal having any one of first to third signal levels based on the data signal, a command decoder configured to receive a feedback signal from outside of the memory device and decode the feedback signal, a data signal controller configured to adjust the data signal based on a decoding result of the command decoder, and a drive strength controller configured to adjust at least one of the first to third signal levels based on the decoding result of the command decoder.

Abstract: The present disclosure relates to a device and method for detecting vertical misalignment of a vehicle radar device and vehicle radar device with the same. A radar device according to an embodiment determines a monitoring range including the ground in front by using the radar signal, determines an error of vertical angles for a number of ground distances within the monitoring range, and detects the vertical mounting misalignment of the radar device by using the error. According to embodiments, it is possible to accurately determine the vertical mounting misalignment of the radar device even if there is a road surface non-uniformity, road slope, or radar beam width change.

Abstract: A semiconductor device including an error amplifier configured to receive a voltage of an output node and a reference voltage, a flipped voltage follower (FVF) circuit configured to receive an output of the error amplifier and maintain the voltage of the output node at the reference voltage, and a bias current control circuit configured to receive first to third mode signals, control a magnitude of a bias current flowing through the FVF circuit based on the first to third mode signals, control the bias current of a first magnitude, based on the first mode signal, control the bias current of a second magnitude smaller than the first magnitude, based on the second mode signal, and control the bias current of a third magnitude smaller than the second magnitude, based on the third mode signal.

Abstract: An inductor according to an embodiment of the present invention may include: a plurality of first E-type cores, each of which has a base unit and a center leg extending in a first direction from the base unit; a first I-type core arranged in the first direction from the plurality of first E-type cores; and a coil wound around the center leg of each of the plurality of first E-type cores. Here, the plurality of E-type cores may be arranged in a line along the first direction.

Abstract: A memory device in which reliability of a clock signal is improved is provided. The memory device comprises a data module including a clock signal generator configured to receive an internal clock signal from a buffer, and to generate a first internal clock signal, a second internal clock signal, a third internal clock signal, and a fourth internal clock signal having different phases, on the basis of the internal clock signal, and a first data signal generator configured to generate a first data signal on the basis of first data and the first internal clock signal, generate a second data signal on the basis of second data and the second internal clock signal, generate a third data signal on the basis of third data and the third internal clock signal, and generate a fourth data signal on the basis of fourth data and the fourth internal clock signal.

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

Abstract: Aspects of the disclosed technology include techniques, mechanism, and a battery management apparatus for diagnosing battery cells that may experience under-voltage. The battery management apparatus may determine a cumulative balancing time of each battery cell of a plurality of battery cells included in a battery pack. The battery management system may determine whether the battery pack is abnormal by comparing a median of the cumulative balancing times of each of the plurality of battery cells with a first reference time. The battery management apparatus may identify at least one under-voltage battery cell of the plurality of battery cells by comparing the cumulative balancing time of each of the plurality of battery cells with a second reference time when the median exceeds the first reference time.

Abstract: The present invention relates to a novel naphthyridinone derivative compound, a pharmaceutically acceptable salt thereof, a hydrate thereof, or a stereoisomer thereof, which are each relevant to a compound for inhibiting ENPP1, a composition for inhibiting ENPP1, and a method for inhibiting ENPP1.

Abstract: The present invention relates to a novel benzotriazole derivative compound, a tautomer thereof, a pharmaceutically acceptable salt thereof, a hydrate thereof, or a stereoisomer thereof, which are related to a compound for inhibiting ENPP1, a composition for inhibiting ENPP1, and a method for inhibiting ENPP1.

Abstract: A data receiving device may include a dummy stage block. The dummy stage block may include m dummy stages, wherein m is a natural number greater than or equal to two. Each of the m dummy stages may be configured to remove inter-symbol interference (ISI) from a dummy input signal using dummy coefficient information to generate a dummy output signal free of the ISI. Each of the m dummy stages may be further configured to output the dummy output signal. A normal stage block may include n normal stages, wherein n is a natural number greater than or equal to two. Each of the n normal stages may be configured to remove ISI from an input signal using coefficient information to generate an output signal free of the ISI and may be further configured to output the output signal.