Patents by Inventor Jung-Hwan Oh

Jung-Hwan Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040224498
    Abstract: A contact structure includes a lower conductive pattern disposed on a predetermined region of a semiconductor substrate. The lower conductive layer has a concave region at a predetermined region of a top surface thereof. An embedding conductive layer fills the concave region. The top surface of the embedding conductive layer is placed at least as high as the height of the flat top surface of the lower conductive pattern. A mold layer is disposed to cover the semiconductor substrate, the lower conductive pattern and the embedding conductive layer. An upper conductive pattern is arranged in an intaglio pattern. The intaglio pattern is disposed in the mold layer to expose a predetermined region of the embedding conductive layer.
    Type: Application
    Filed: April 28, 2004
    Publication date: November 11, 2004
    Applicant: SAMSUNG ELECTRONICS CO., LTD
    Inventors: Jung-Hwan Oh, Byung-Lyul Park, Hong-Seong Son
  • Publication number: 20040224532
    Abstract: In a method of forming an oxide layer, ozone is generated by reacting an oxygen gas having a first flow rate with a nitrogen gas having a second flow rate of more than about 1% of the first flow rate. A reactant including the ozone and nitrogen is provided onto a silicon substrate. A surface of the silicon substrate is oxidized via the reaction of the reactant with silicon in the silicon substrate. The flow rate of the nitrogen gas is increased while ozone serving as an oxidant is formed by reacting the nitrogen gas with the oxygen gas. Thus, the oxide layer or a metal oxide layer including nitrogen may be rapidly formed on the substrate.
    Type: Application
    Filed: May 5, 2004
    Publication date: November 11, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Won-Sik Shin, Ki-Hyun Hwang, Jung-Hwan Oh, Hyeon-Deok Lee, Seok-Woo Nam
  • Publication number: 20040085708
    Abstract: An etch stop layer is formed over a surface of an interlayer insulating layer and over a surface of a conductive plug extending at a depth from the surface of the interlayer insulating layer. A lower mold layer is deposited over the etch stop layer, and a wet etch rate of the lower mold layer is adjusted by adding dopants to the lower mold layer during formation of the lower mold layer, and by annealing the lower mold layer. An upper mold layer is then deposited over the surface of the lower mold layer, such that a wet etch rate of the upper mold layer is less than the adjusted wet etch rate of the lower mold layer. The upper mold layer, the lower mold layer and the etch stop layer are then subjected to dry etching to form an opening therein which exposes at least a portion of the surface of the contact plug.
    Type: Application
    Filed: October 20, 2003
    Publication date: May 6, 2004
    Inventors: Jung-Hwan Oh, Ki-Hyun Hwang, Jae-Young Park, In-Seak Hwang, Young-Wook Park
  • Patent number: 6700153
    Abstract: An etch stop layer is formed over a surface of an interlayer insulating layer and over a surface of a conductive plug extending at a depth from the surface of the interlayer insulating layer. A lower mold layer is deposited over the etch stop layer, and a wet etch rate of the lower mold layer is adjusted by adding dopants to the lower mold layer during formation of the lower mold layer, and by annealing the lower mold layer. An upper mold layer is then deposited over the surface of the lower mold layer, such that a wet etch rate of the upper mold layer is less than the adjusted wet etch rate of the lower mold layer. The upper mold layer, the lower mold layer and the etch stop layer are then subjected to dry etching to form an opening therein which exposes at least a portion of the surface of the contact plug.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: March 2, 2004
    Assignee: Samsung Electronics Co. Ltd.
    Inventors: Jung-Hwan Oh, Ki-Hyun Hwang, Jae-Young Park, In-Seak Hwang, Young-Wook Park
  • Publication number: 20030121132
    Abstract: An etch stop layer is formed over a surface of an interlayer insulating layer and over a surface of a conductive plug extending at a depth from the surface of the interlayer insulating layer. A lower mold layer is deposited over the etch stop layer, and a wet etch rate of the lower mold layer is adjusted by adding dopants to the lower mold layer during formation of the lower mold layer, and by annealing the lower mold layer. An upper mold layer is then deposited over the surface of the lower mold layer, such that a wet etch rate of the upper mold layer is less than the adjusted wet etch rate of the lower mold layer. The upper mold layer, the lower mold layer and the etch stop layer are then subjected to dry etching to form an opening therein which exposes at least a portion of the surface of the contact plug.
    Type: Application
    Filed: May 2, 2002
    Publication date: July 3, 2003
    Inventors: Jung-Hwan Oh, Ki-Hyun Hwang, Jae-Young Park, In-Seak Hwang, Young-Wook Park