Abstract: Silicon oxide-based negative electrode active materials and negative electrodes for a secondary battery are disclosed. In an embodiment, a negative electrode active material for a secondary battery includes a silicon oxide particle including a metal silicate; and a hydrocarbon coating layer on the silicon oxide particle, wherein a peak Pa in a Fourier transform infrared (FT-IR) spectral analysis of the negative electrode active material is detected in a range from 2880 cm?1 to 2950 cm?1 and a peak Pb in a FT-IR spectral analysis of the negative electrode active material is detected in a range from 2800 cm?1 to 2865 cm?1.

Abstract: The present invention relates to an antigen-binding molecule comprising a heavy chain variable region comprising a heavy-chain complementarity-determining region 1 (HCDR1) comprising an amino acid sequence represented by Sequence No. 1, an HCDR2 comprising an amino acid sequence represented by Sequence No. 2, and an HCDR3 comprising an amino acid sequence represented by Sequence No. 3; a light-chain variable region comprising a light-chain complementarity-determining region 1 (LCDR1) comprising an amino acid sequence represented by Sequence No. 4, an LCDR2 comprising an amino acid sequence represented by Sequence No. 5, and an LCDR3 comprising an amino acid sequence represented by Sequence No. 6; wherein the antigen-binding molecule is a T cell receptor (TCR); and to a cell line expressing the same.

Abstract: Disclosed are novel compounds of Chemical Formula 1, optical isomers of the compounds, and pharmaceutically acceptable salts of the compounds or the optical isomers. The compounds, isomers, and salts exhibit excellent activity as GLP-1 receptor agonists. In particular, they, as GLP-1 receptor agonists, exhibit excellent glucose tolerance, thus having a great potential to be used as therapeutic agents for metabolic diseases. Moreover, they exhibit excellent pharmacological safety for cardiovascular systems.

Abstract: Provided are a method and apparatus for encoding or decoding a coding unit on an outline of a picture. An image decoding method and apparatus according to an embodiment determine whether a current coding unit extends across an outline of a picture, by comparing a location of the current coding unit in the picture to at least one of a width and a height of the picture, split the current coding unit in at least one direction into a plurality of coding units based on a shape of the current coding unit upon determining that the current coding unit extends across the outline of the picture, obtain block shape information and split type information of the current coding unit from a bitstream and split the current coding unit into a plurality of coding units based on the block shape information and the split type information upon determining that the current coding unit does not extend across the outline of the picture, and decode a coding unit that is no longer split among the plurality of coding units.

Abstract: An image sensor is provided. The An image sensor includes: a first substrate including a first side and a second side opposite to each other, and an active region; a plurality of pixel regions, each including a photoelectric conversion layer on the first side of the first substrate; a pixel isolation pattern which separates the plurality of pixel regions from each other and extends along a direction perpendicular to the first side of the first substrate; and a first transistor, a second transistor and a third transistor corresponding to a first pixel region of the plurality of pixel regions. The first transistor, the second transistor and the third transistor share a common source/drain region inside the active region.

Abstract: An integrated circuit (IC) device includes an optical IC substrate, a local trench inside the optical IC substrate, and a photoelectronic element including a photoelectric conversion layer buried inside the local trench. The photoelectric conversion layer is buried inside the local trench in the optical IC substrate to form the photoelectronic element. Thus, the IC device may inhibit warpage of the optical IC substrate.

Abstract: An integrated circuit (IC) device includes an optical IC substrate, a local trench inside the optical IC substrate, and a photoelectronic element including a photoelectric conversion layer buried inside the local trench. The photoelectric conversion layer is buried inside the local trench in the optical IC substrate to form the photoelectronic element. Thus, the IC device may inhibit warpage of the optical IC substrate.

Abstract: An integrated circuit (IC) device includes an optical IC substrate, a local trench inside the optical IC substrate, and a photoelectronic element including a photoelectric conversion layer buried inside the local trench. The photoelectric conversion layer is buried inside the local trench in the optical IC substrate to form the photoelectronic element. Thus, the IC device may inhibit warpage of the optical IC substrate.

Abstract: An integrated circuit (IC) device includes an optical IC substrate, a local trench inside the optical IC substrate, and a photoelectronic element including a photoelectric conversion layer buried inside the local trench. The photoelectric conversion layer is buried inside the local trench in the optical IC substrate to form the photoelectronic element. Thus, the IC device may inhibit warpage of the optical IC substrate.

Abstract: An optical device includes a substrate; a trench in a portion of the substrate; a clad layer arranged in the trench; a first structure arranged on the clad layer to have a first depth; and a second structure arranged on the clad layer to have a second depth different from the first depth.

Abstract: An optical device includes a substrate; a trench in a portion of the substrate; a clad layer arranged in the trench; a first structure arranged on the clad layer to have a first depth; and a second structure arranged on the clad layer to have a second depth different from the first depth.

Abstract: A method of manufacturing a semiconductor apparatus includes forming a gate structure and an etch stop layer structure on a substrate including first and second regions. The gate structure is formed in the first region, and the etch stop layer structure is formed in the second region. A first insulating interlayer is formed on the substrate to cover the gate structure and the etch stop layer structure. The first insulating interlayer is partially removed to expose the etch stop layer structure. The exposed etch stop layer is removed to expose the substrate. An optical device is formed on the exposed substrate.

Abstract: A semiconductor substrate having a reference semiconductor chip and a method of assembling semiconductor chips using the same are provided. According to the method, a semiconductor substrate having a plurality of semiconductor chips is provided. An identification mark is made on a reference semiconductor chip among the semiconductor chips. The semiconductor substrate is aligned with reference to the reference semiconductor chip, so that an electrical die sorting test can be performed on the semiconductor chips on the semiconductor substrate.

Abstract: A digital test apparatus for testing an analog semiconductor device includes a low pass filter which passes only a low frequency analog signal from among analog signals output from the analog semiconductor device, a rectifying unit connected to the low pass filter for converting the analog signal output from the low pass filter into a DC voltage, a high pass filter which passes only a high frequency analog signal from among analog signals output from the analog semiconductor device, a high frequency power detecting unit connected to the high pass filter for converting the analog signal output from the high pass filter into a DC voltage, and a digital measuring unit which is connected to the rectifying unit and the high frequency power detecting unit and measures the DC voltages to determine whether the analog signals output from the analog semiconductor device are desirable.

Abstract: An apparatus for generating a current source test stimulus signal having a constant current regardless of an internal impedance value of a device under test includes a voltage source generation unit and a voltage to current (V/I) converter. The voltage source generation unit converts source data stored in internal memory into analog signals, and combines the analog signals and a reference signal of D/C voltage level to generate voltage source test stimulus signals. The V/I converter converts the voltage source test stimulus signals into current source test stimulus signals and outputs the current source test stimulus signal to a device under test. The V/I converter maintains the current levels of the current source test stimulus signals at a predetermined value, regardless of the internal impedance of input pins of the device under test. In this manner, the operating efficiency of the device under test can be accurately determined.

Abstract: Provided are an integrated circuit (IC) package having balls designed to minimize contact resistance, a test apparatus for testing the IC package, and a method of manufacturing the IC package. The IC package is a ball grid array (BGA) package including solder balls, the solder balls having substantially flat bottoms. The balls of the BGA package are Pb-free balls, and are polished using a mechanical polishing method or a chemical polishing method to have the substantially flat bottoms. The test apparatus includes a plurality of channels, a test board having a wiring pattern connected to the channels, and an IC socket having a plurality of Pogo pins respectively connected to lands of the wiring pattern. The top ends of the Pogo pins of the IC socket are made substantially flat to increase the area that contacts the substantially flat bottom surfaces of the BGA package.

Abstract: A digital test apparatus for testing an analog semiconductor device includes a low pass filter which passes only a low frequency analog signal from among analog signals output from the analog semiconductor device, a rectifying unit connected to the low pass filter for converting the analog signal output from the low pass filter into a DC voltage, a high pass filter which passes only a high frequency analog signal from among analog signals output from the analog semiconductor device, a high frequency power detecting unit connected to the high pass filter for converting the analog signal output from the high pass filter into a DC voltage, and a digital measuring unit which is connected to the rectifying unit and the high frequency power detecting unit and measures the DC voltages to determine whether the analog signals output from the analog semiconductor device are desirable.

Abstract: A semiconductor substrate having a reference semiconductor chip and a method of assembling semiconductor chips using the same are provided. According to the method, a semiconductor substrate having a plurality of semiconductor chips is provided. An identification mark is made on a reference semiconductor chip among the semiconductor chips. The semiconductor substrate is aligned with reference to the reference semiconductor chip, so that an electrical die sorting test can be performed on the semiconductor chips on the semiconductor substrate.

Abstract: An apparatus for generating a current source test stimulus signal having a constant current regardless of an internal impedance value of a device under test includes a voltage source generation unit and a voltage to current (V/I) converter. The voltage source generation unit converts source data stored in internal memory into analog signals, and combines the analog signals and a reference signal of D/C voltage level to generate voltage source test stimulus signals. The V/I converter converts the voltage source test stimulus signals into current source test stimulus signals and outputs the current source test stimulus signal to a device under test. The V/I converter maintains the current levels of the current source test stimulus signals at a predetermined value, regardless of the internal impedance of input pins of the device under test. In this manner, the operating efficiency of the device under test can be accurately determined.