Abstract: Disclosed are a hinge unit which couples a first member and a second member, the hinge unit including: a conic shaft which is coupled to the first member, and comprises a hinge pivot, a conic unit of a truncated cone shape, the radius of which is extended in an end area of the hinge pivot, and a first rocking unit formed to an outer surface of the conic unit; and a conic sleeve which is coupled to the second member, and comprises a sleeve main body formed with a conic accommodating unit having a shape corresponding to the conic unit in an inner part of the conic accommodating unit, and a second rocking unit formed to an inner surface of the conic accommodating unit to be coupled with the first rocking unit.

Abstract: A semiconductor memory device includes a first conductive line on a semiconductor substrate, an interlayer insulating layer on the first conductive line, a second conductive line on the interlayer insulating layer, and a memory cell in an hole through the interlayer insulating layer wherein the first and second conductive lines cross, the memory cell including a discrete resistive memory material region disposed in the hole and electrically connected between the first and second conductive lines. The resistive memory material region may be substantially contained within the hole. In some embodiments, contact between the resistive memory material region and the interlayer insulating layer is substantially limited to sidewalls of the interlayer insulating layer in the hole.

Abstract: A semiconductor device includes a semiconductor package, a circuit board and an interval maintaining member. The semiconductor package has a body and a lead protruded from the body. The circuit board has a first land electrically connected to the lead. The interval maintaining member is interposed between the circuit board and the body. The interval maintaining member maintains an interval between the lead and the first land. Thus, an interval between the lead and the land is uniformly maintained, so that a thermal and/or mechanical reliability of the semiconductor device is improved.

Abstract: A vacuum type pickup apparatus may include an absorption pad having an absorption inlet for contacting and/or picking up an object. A pad holder may be connected to the absorption pad. The pad holder may also have a vacuum line. A separator may be provided in the pad holder for forcibly releasing the object from the absorption inlet of the absorption pad. During the forcible release of the object, the air around the absorption pad may be drawn into the pad holder, thus reducing or preventing the potential contamination by impurities of the object as well as the equipment around the object. Also, an additional vacuum extinguisher may not be required, thus simplifying the structure of the vacuum type pickup apparatus and reducing installation costs. Furthermore, the object may be picked up and released in a relatively expedient, safe, and accurate manner, despite the suction force of the vacuum that may be maintained in the pad holder.

Abstract: In a method of forming a wiring having a carbon nanotube, a lower wiring is formed on a substrate, and a catalyst layer is formed on the lower wiring. An insulating interlayer is formed on the substrate to cover the catalyst layer, and an opening is formed through the insulating interlayer to expose an upper face of the catalyst layer. A carbon nanotube wiring is formed in the opening, and an upper wiring is formed on the carbon nanotube wiring and the insulating interlayer to be electrically connected to the carbon nanotube wiring. A thermal stress is generated between the carbon nanotube wiring and the upper wiring to produce a dielectric breakdown of a native oxide layer formed on a surface of the carbon nanotube wiring. A wiring having a reduced electrical resistance between the carbon nanotube wiring and the upper wiring may be obtained.

Abstract: A complementary metal-oxide-semiconductor image sensor may include: a semiconductor substrate; a photodiode formed on a first portion of the semiconductor substrate; a transfer gate formed on the semiconductor substrate, near the photodiode, to transfer optical charges accumulated in the photodiode; a floating diffusion area formed on a second portion of the semiconductor substrate, on an opposite side of the transfer gate from the photodiode, to accommodate the optical charges; and/or a channel area formed under the transfer gate and contacting a side of the photodiode to transfer the optical charges. The transfer gate may be formed, at least in part, of transparent material. A method of manufacturing a complimentary metal-oxide-semiconductor image sensor may include: forming the photodiode; forming the floating diffusion area, separate from the photodiode; and/or forming the transfer gate, near the photodiode, to transfer optical charges accumulated in the photodiode.

Abstract: A capacitor structure includes an insulating layer, first conductive patterns, second conductive patterns, an insulating interlayer, third conductive patterns, and fourth conductive patterns. The first and second conductive patterns are alternately arranged on the insulating layer to be spaced apart from one another. The first and second conductive patterns have side faces where concave portions and convex portions are formed. The insulating interlayer is formed on the insulating layer to cover the first and second conductive patterns. The third and fourth conductive patterns are alternately arranged on the insulating interlayer to be spaced apart from one another. The third and fourth conductive patterns have side faces where concave portions and convex portions are formed.

Abstract: The present invention relates to a backlight assembly and a liquid crystal display (“LCD”) having the same. The backlight assembly includes a light source unit including a printed circuit board (“PCB”) and a plurality of light emitting diodes (“LEDs”) mounted on a side of the PCB, a receiving member including a base plate and a plurality of walls that extend from the base plate at an angle and receive the light source unit, and a plurality of through holes or uneven patterns formed in a region of the receiving member where at least the light source unit is disposed.

Abstract: A wire clamp includes a pair of clamp arms at a predetermined distance from each other to define an interval therebetween for a bonding wire, a clamp body coupled to the clamp arms, the clamp body configured to adjust the predetermined distance between the clamp arms with respect to a process to be performed, a clamping section in each clamp arm, the clamping section having concave portions facing the interval between the clamp arms, the concave portions being configured to contact the bonding wire when the clamp arms are brought close together, and at least one abrasion prevention member in each clamping section, the abrasion prevention members being configured to prevent abrasion during contact with the bonding wire.

Abstract: A projection-type display apparatus and a display method thereof are disclosed, the projection-type display apparatus including a coated portion which is formed on a surface of a substrate, and which scans a video onto a screen, and a patterned portion which is formed on another surface of the substrate in a serrated pattern, wherein the serrated pattern is formed on the substrate according to the surface area of the patterned portion and the depth of the serrated pattern. A serrated pattern is formed on a substrate forming a reflective portion to reflect a video on a screen, so the cooling surface area of the substrate is increased, thereby compensating for distortions in video scanned onto the screen.

Abstract: A data line layout includes column selection lines arranged in a first direction at a layer on a memory cell array region, and data lines arranged in the first direction at the layer, the data lines being connected between I/O sense amplifiers and I/O pads.

Abstract: A method of forming an information storage pattern, includes placing a semiconductor substrate in a process chamber, injecting first, second and third process gases into the process chamber during a first process to form a lower layer on the substrate based on a first injection time and/or a first pause time, injecting the second process gas into the process chamber during a second process, wherein the second process gas is injected into the process chamber during a first elimination time, injecting a fourth process gas together with the second and third process gases into the process chamber during a third process in accordance with a second injection time and/or a second pause time to form an upper layer on the lower layer, and injecting the second process gas into the process chamber during a fourth process, wherein the second process gas is injected into the process chamber during a second elimination.

Abstract: Provided are methods of forming a phase change memory device. A semiconductor device having a lower electrode and an interlayer insulating layer may be prepared. The lower electrode may be surrounded by the interlayer insulating layer. Source gases, a reaction gas and a purge gas may be injected into a process chamber of a semiconductor fabrication device to form a phase change material layer on a semiconductor substrate. The source gases may be simultaneously injected into the process chamber. The phase change material layer may be in contact with the lower electrode through the interlayer insulating layer. The phase change material layer may be etched to form a phase change memory cell in the interlayer insulating layer. An upper electrode may be formed on the phase change memory cell.

Abstract: A casing to support a solid state device SSD therein and super capacitors therein to be electronically connected together.

Abstract: A hard disk drive, in which a flexible printed circuit board (FPC) bracket is readily assembled and sealed to a base together with a gasket header even though a screw or a sealing tape that involves a screw driver or other assembling tools is not used, or a boss of the base is not tapped.

Abstract: A lead frame unit, a semiconductor package having a lead frame unit, a stacked semiconductor package having a semiconductor package, and methods of manufacturing the same are provided. The lead frame unit in a stacked semiconductor package may include a die pad supporting a semiconductor chip, an inner lead electrically connected to the semiconductor chip, an outer lead extending from the inner lead, and a heat-resistant insulation member surrounding the connection portion. The outer lead may include a connection portion connected to the inner lead and a junction portion connected to the connection portion and a circuit board. An external signal may be applied to the junction portion. If the lead frame unit is used in the stacked semiconductor package, the outer lead and a dummy outer lead in the stacked semiconductor package may have substantially the same shape.

Abstract: There is provided a multilayer type test board assembly for high-precision inspection. The multilayer test board assembly comprises: a plurality of test boards separated from each other according to their functions, having input/output signal terminals, and including at least one test board each having a first section where first mounting devices sensitive to an influence of electrical signals are mounted and a second section where second mounting devices insensitive to an influence of electrical signals are mounted; spacers that arrange the test boards in parallel by spacing apart the test boards by predetermined intervals; connection cables connected to the input/output signal terminals of the test boards; and a signal shielding fence formed on each of the at least one test board so as to protect the first mounting devices from electrical signals generated by the second mounting devices.

Abstract: In a capacitor structure and a method of manufacturing the capacitor structure, first and second conductive patterns are formed on a substrate. The first and second conductive patterns extend in a first direction. The first and second conductive patterns are alternately arranged to be spaced apart from one another in a second direction substantially perpendicular to the first direction. An insulating interlayer is formed on the substrate to cover the first and second conductive patterns. Third and fourth conductive patterns extending in a third direction lying at an angle of between about 0° and about 90° relative to the first direction are formed on the insulating interlayer. The third and fourth conductive patterns are alternately arranged to be spaced apart from one another in a fourth direction substantially perpendicular to the third direction.

Abstract: An IC package including a plurality of BGA IC packages stacked on a printed circuit board and a method of manufacturing the same. The IC package includes a printed circuit board, a first BGA IC package, having a plurality of first solder balls, stacked on the printed circuit board, a second BGA IC package, having a plurality of second solder balls, stacked on the first BGA IC package, and an interposer having a plurality of through-holes, which are filled by the second solder balls in a molten state such that the length of the second solder balls increases while the second solder balls harden, the interposer being joined to the top of the first BGA IC package.

Abstract: Disclosed is a ball land structure suitable for use with a semiconductor package. The ball land structure includes a ball land and a barrier on a core. The barrier may be configured to connect to the ball land so as to form a barrier hole between an edge of the ball land and an edge of the barrier thus exposing a portion of the core. A solder mask may be deposited on the ball land and a portion of the core exposed by the barrier hole so as to partially expose the core.