Patents by Inventor Jung-hyeon Lee
Jung-hyeon Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Adhesive protective film, optical member comprising the same and optical display comprising the same
Patent number: 11958993Abstract: Disclosed herein are an adhesive protective film, an optical member including the same, and an optical display including the same. An adhesive protective film is formed of a composition including a (meth)acrylic binder derived from a monomer mixture including: an alkyl group-containing (meth)acrylic monomer; and at least one selected from among a hydroxyl group-containing (meth)acrylic monomer, a carboxyl group-containing (meth)acrylic monomer, and a polysiloxane (meth)acrylate, the adhesive protective film having an initial peel strength of about 100 gf/inch or less and a peel strength decrease rate of about 50% or less, as calculated according to Equation 1.Type: GrantFiled: May 27, 2021Date of Patent: April 16, 2024Assignee: Samsung SDI Co., Ltd.Inventors: Irina Nam, Tae Ji Kim, Won Kim, Il Jin Kim, Jung Hyo Lee, Oh Hyeon Hwang -
Patent number: 11956426Abstract: Disclosed herein are a decoding method and apparatus and an encoding method and apparatus for deriving an intra-prediction mode. An intra-prediction mode may be derived using a method for deriving an intra-prediction mode based on a neighbor block of the target block, a method for deriving an intra-prediction mode using signaling of the intra-prediction mode of the target block, or a method for deriving an adaptive intra-prediction mode based on the type of a target slice. An MPM list may be used to derive the intra-prediction mode, and a temporal neighbor block or the like may be used to configure the MPM list.Type: GrantFiled: May 9, 2022Date of Patent: April 9, 2024Assignees: Electronics and Telecommunications Research Institute, Industry-University Cooperation Foundation Korea Aerospace University, Industry-Academia Cooperation Group of Sejong UniversityInventors: Jin-Ho Lee, Jae-Gon Kim, Jung-Won Kang, Do-Hyeon Park, Yung-Lyul Lee, Ha-Hyun Lee, Sung-Chang Lim, Hui-Yong Kim, Ji-Hoon Do, Yong-Uk Yoon
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Publication number: 20240112864Abstract: A method of manufacturing a multilayer electronic component includes cutting a stack, in which internal electrode patterns and ceramic green sheets are alternately stacked in a stacking direction, to obtain unit chips and attaching a portion of a ceramic green sheet for a side margin portion to the unit chips in a direction, different from the stacking direction. The attaching includes attaching the portion of the ceramic green sheet to the unit chips by compression between a first elastic body on which the ceramic green sheet is disposed and the unit chips. The first elastic body includes a first elastic layer having and a second elastic layer having an elastic modulus different from the first elastic layer, and disposed between the unit chips and the first elastic layer. An elastic modulus of the first elastic body is greater than 50 MPa and less than or equal to 1000 MPa.Type: ApplicationFiled: July 10, 2023Publication date: April 4, 2024Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Yong PARK, Jung Tae PARK, Jong Ho LEE, Eun Jung LEE, Yong Min HONG, Jung Jin PARK, Rak Hyeon BAEK, Sun Mi KIM, Yong Ung LEE
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Publication number: 20240104195Abstract: Disclosed herein are an apparatus and method for updating an Internet-based malware detection engine using virtual machine scaling. The method may include creating a scaling group and an update group set based on a first virtual machine image, creating a second virtual machine image for a running virtual machine in response to occurrence of a snapshot event in the virtual update group run based on the first virtual machine image, modifying the scale-out image of the scaling group to the second virtual machine image, updating the scaling group by triggering a scale-out event and a scale-in event in the scaling group in response to occurrence of an update event, and modifying the scale-in image of the scaling group to the second virtual machine image.Type: ApplicationFiled: June 15, 2023Publication date: March 28, 2024Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sang-Min LEE, Ki-Jong KOO, Jung-Tae KIM, Ji-Hyeon SONG, Jong-Hyun KIM, Dae-Sung MOON
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Publication number: 20240088440Abstract: A lithium secondary battery includes a negative electrode, a positive electrode positioned opposite to the negative electrode, a separator disposed between the negative electrode and the positive electrode, and a non-aqueous electrolyte, wherein the negative electrode includes a silicon-based active material, the silicon-based active material comprises a compound represented by SiOx, wherein 0?x<2, the non-aqueous electrolyte includes a lithium salt, an organic solvent, and an additive, the additive includes a first additive and a second additive, the first additive includes a coumarin-based compound represented by Formula 1, and the second additive includes at least one of lithium fluoromalonato(difluoro)borate (LiFMDFB), lithium difluoro(oxalato)borate (LiDFOB), lithium difluorophosphate (LiDFP), or lithium difluorobis-(oxalate)phosphate (LiDFOP): wherein R and n are described herein.Type: ApplicationFiled: August 17, 2023Publication date: March 14, 2024Applicant: LG Energy Solution, Ltd.Inventors: Yoon Gyo Cho, Chul Haeng Lee, Kyung Mi Lee, Jung Min Lee, Eun Bee Kim, Su Hyeon Ji, Chul Eun Yeom, Jung Gu Han
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Patent number: 11930179Abstract: An image encoding/decoding method is provided. An image decoding method of the present invention may comprise deriving an intra-prediction mode of a current luma block, deriving an intra-prediction mode of a current chroma block based on the intra-prediction mode of the current luma block, generating a prediction block of the current chroma block based on the intra-prediction mode of the current chroma block, and the deriving of an intra-prediction mode of a current chroma block may comprise determining whether or not CCLM (Cross-Component Linear Mode) can be performed for the current chroma block.Type: GrantFiled: December 27, 2019Date of Patent: March 12, 2024Assignees: Electronics and Telecommunications Research Institute, INDUSTRY ACADEMY COOPERATION FOUNDATION OF SEJONG UNI, CHIPS & MEDIA, INC, INDUSTRY-UNIVERSITY COOPERATION FOUNDATION KOREA AEROSPACE UNIVERSITYInventors: Sung Chang Lim, Jung Won Kang, Ha Hyun Lee, Jin Ho Lee, Hui Yong Kim, Yung Lyul Lee, Ji Yeon Jung, Nam Uk Kim, Myung Jun Kim, Yang Woo Kim, Dae Yeon Kim, Jae Gon Kim, Do Hyeon Park
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Patent number: 11919122Abstract: A substrate processing apparatus includes: a conveyor belt configured to have an outer surface on which a bottom surface of a substrate is seated; and a polishing head unit configured to face an upper surface of the substrate, wherein the polishing head unit includes: a polishing head connected to a driver; a polishing pad configured to face the polishing head; a polishing pad fixing ring disposed between the polishing head and the polishing pad; and a temperature sensor configured to overlap the polishing pad fixing ring and to be spaced apart from the polishing pad fixing ring.Type: GrantFiled: September 29, 2020Date of Patent: March 5, 2024Assignees: SAMSUNG DISPLAY CO., LTD., KCTECH CO., LTD.Inventors: Seung Bae Kang, Sung Hyeon Park, Jung Gun Nam, Joon-Hwa Bae, Kyung Bo Lee, Keun Woo Lee, Woo Jin Cho, Byoung Kwon Choo
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Patent number: 8778598Abstract: A method of forming fine patterns of a semiconductor device according to a double patterning process that uses acid diffusion is provided. In this method, a plurality of first mask patterns are formed on a substrate. A capping film including an acid source is formed on the exposed surface areas of the plurality of first mask patterns. A second mask layer is formed on the capping films. A plurality of acid diffused regions are formed within the second mask layer by diffusing acid obtained from the acid source from the capping films into the second mask layer. A plurality of second mask patterns are formed of residual parts of the second mask layer which remain after removing the acid diffused regions of the second mask layer.Type: GrantFiled: December 12, 2012Date of Patent: July 15, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Yool Kang, Suk-joo Lee, Jung-hyeon Lee, Shi-yong Yi
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Patent number: 8431331Abstract: A method of forming fine patterns of a semiconductor device according to a double patterning process that uses acid diffusion is provided. In this method, a plurality of first mask patterns are formed on a substrate so as to be separated from one another. A capping film including an acid source is formed on sidewalls and an upper surface of each of the plurality of first mask patterns. A second mask layer is formed on the capping films. A plurality of acid diffused regions are formed within the second mask layer by diffusing acid obtained from the acid source from the capping films into the second mask layer. A plurality of second mask patterns are formed of residual parts of the second mask layer which remain in the first spaces after removing the acid diffused regions of the second mask layer.Type: GrantFiled: November 10, 2008Date of Patent: April 30, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Yool Kang, Suk-joo Lee, Jung-hyeon Lee, Shi-yong Yi
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Patent number: 7892982Abstract: A method for forming fine patterns of a semiconductor device includes forming an etching film on a substrate having first and second areas, forming first mask patterns on the substrate to have a first pattern density in the first area and a second pattern density in the second area, forming first capping patterns between the first mask patterns, forming second capping patterns between the first mask patterns, such that recess areas are formed between second capping patterns, and such that a first etching pattern is defined to include the first and second capping patterns, forming second mask patterns in the recess areas to include the first and second mask patterns, removing one of the first and second etching patterns, such that a single etching pattern is remaining on the substrate, and etching the etching film using the remaining etching pattern as an etch mask to form etching film patterns.Type: GrantFiled: October 30, 2007Date of Patent: February 22, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Doo-youl Lee, Pan-suk Kwak, Sung-gon Jung, Jung-hyeon Lee, Suk-joo Lee, Cha-won Koh, Ji-young Lee
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Patent number: 7670761Abstract: In a resist reflow measurement key, and method of fabricating a fine pattern of a semiconductor device using the same, the resist reflow measurement key includes a first reflow key including a plurality of first pattern elements each having a first pattern with a first radius of curvature located on a first side of a first center line and a second pattern with a second radius of curvature located on a second side of the first center line, and a second reflow key including a plurality of second pattern elements each having a third pattern with a third radius of curvature located on a first side of a second center line and a fourth pattern with a fourth radius of curvature located on a second side of the second center line, the second reflow key being formed on a same plane of a substrate as the first reflow key.Type: GrantFiled: July 17, 2008Date of Patent: March 2, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Doo-youl Lee, Gi-sung Yeo, Han-ku Cho, Jung-hyeon Lee
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Publication number: 20090274980Abstract: A method of forming fine patterns of a semiconductor device according to a double patterning process that uses acid diffusion is provided. In this method, a plurality of first mask patterns are formed on a substrate so as to be separated from one another. A capping film including an acid source is formed on sidewalls and an upper surface of each of the plurality of first mask patterns. A second mask layer is formed on the capping films. A plurality of acid diffused regions are formed within the second mask layer by diffusing acid obtained from the acid source from the capping films into the second mask layer. A plurality of second mask patterns are formed of residual parts of the second mask layer which remain in the first spaces after removing the acid diffused regions of the second mask layer.Type: ApplicationFiled: November 10, 2008Publication date: November 5, 2009Inventors: Yool Kang, Suk-joo Lee, Jung-hyeon Lee, Shi-yong Yi
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Patent number: 7473497Abstract: A phase shifting mask (PSM) for manufacturing a semiconductor device and a method of fabricating the same includes a transparent substrate, a main pattern formed on the transparent substrate and comprising a first phase shifting layer having a first optical transmittance greater than 0, and at least one assistant pattern formed on the transparent substrate proximal to the main pattern for phase-shifting by the same degree as the main pattern and having a second optical transmittance, which is less than the first optical transmittance.Type: GrantFiled: March 18, 2005Date of Patent: January 6, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: In-sung Kim, Jung-hyeon Lee, Sung-gon Jung
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Patent number: 7457058Abstract: In an optical member holder and a projection exposure apparatus having the same, a light beam radiated from a light source may be formed into light having a desired shape by selecting one of a plurality of optical elements. An optical element holder may include a support member to support the plurality of optical elements, a first driving section to move or rotate the support member to select one of the optical elements, and a second driving section to rotate the selected optical element to adjust an arrangement direction thereof. The light formed by the selected optical element may be directed through a reticle.Type: GrantFiled: June 13, 2006Date of Patent: November 25, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Woo-Seok Shim, Jung-Hyeon Lee, Young-Koog Han, Kwang-Sub Yoon, Si-Hyeung Lee
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Publication number: 20080280381Abstract: In a resist reflow measurement key, and method of fabricating a fine pattern of a semiconductor device using the same, the resist reflow measurement key includes a first reflow key including a plurality of first pattern elements each having a first pattern with a first radius of curvature located on a first side of a first center line and a second pattern with a second radius of curvature located on a second side of the first center line, and a second reflow key including a plurality of second pattern elements each having a third pattern with a third radius of curvature located on a first side of a second center line and a fourth pattern with a fourth radius of curvature located on a second side of the second center line, the second reflow key being formed on a same plane of a substrate as the first reflow key.Type: ApplicationFiled: July 17, 2008Publication date: November 13, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Doo-youl Lee, Gi-sung Yeo, Han-ku Cho, Jung-hyeon Lee
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Patent number: 7449383Abstract: In a method of manufacturing a capacitor and a method of manufacturing a dynamic random access memory device, an insulating layer covering an upper portion of a conductive layer may be provided with an ozone gas so as to change the property of the upper portion of the insulating layer. The upper portion of the insulating layer may be chemically removed to expose the upper portion of the conductive layer. The exposed upper portion of the conductive layer may be removed so as to transform the conductive layer into a lower electrode. The remaining portion of the insulating layer may be removed, and an upper electrode may be formed on the lower electrode.Type: GrantFiled: September 14, 2007Date of Patent: November 11, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang-Sub Yoon, Jung-Hyeon Lee, Bong-Cheol Kim, Se-Young Park
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Publication number: 20080230929Abstract: Provided are an overlay mark of a semiconductor device and a semiconductor device including the overlay mark. The overlay mark includes: reference marks formed in rectangular shapes comprising sides in which fine patterns are formed; and comparison marks formed as rectangular shapes which are smaller than the rectangular shapes of the reference marks and formed of fine patterns, wherein the number of comparison marks is equal to the number of reference marks, wherein the reference marks and the comparison marks are formed on different thin films formed on a semiconductor substrate to be used to inspect alignment states of the different thin films, and the overlay mark reflects an effect of aberration of patterns of memory cells through the fine patterns during a calculation of MR (mis-registration).Type: ApplicationFiled: March 5, 2008Publication date: September 25, 2008Inventors: Jang-ho Shin, Chan-hoon Park, Jung-Hyeon Lee, Suk-joo Lee, Hyun-tae Kang, Jeong-hee Cho, Young-hoon Song
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Publication number: 20080124931Abstract: A method for forming fine patterns of a semiconductor device includes forming an etching film on a substrate having first and second areas, forming first mask patterns on the substrate to have a first pattern density in the first area and a second pattern density in the second area, forming first capping patterns between the first mask patterns, forming second capping patterns between the first mask patterns, such that recess areas are formed between second capping patterns, and such that a first etching pattern is defined to include the first and second capping patterns, forming second mask patterns in the recess areas to include the first and second mask patterns, removing one of the first and second etching patterns, such that a single etching pattern is remaining on the substrate, and etching the etching film using the remaining etching pattern as an etch mask to form etching film patterns.Type: ApplicationFiled: October 30, 2007Publication date: May 29, 2008Inventors: Doo-youl Lee, Pan-suk Kwak, Sung-gon Jung, Jung-hyeon Lee, Suk-joo Lee, Cha-won Koh, Ji-young Lee
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Patent number: 7375390Abstract: A semiconductor memory device includes a plurality of rows, each row comprising a plurality of active regions arranged at a pitch wherein the active regions in adjacent rows are shifted with respect to each other by one half of the pitch, wherein a distance between each active region in a row is equal to a distance between active regions in adjacent rows.Type: GrantFiled: January 10, 2007Date of Patent: May 20, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Hyeon Lee, Gi-Sung Yeo, Doo-Hoon Goo, Woo-Sung Han
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Publication number: 20080070361Abstract: In a method of manufacturing a capacitor and a method of manufacturing a dynamic random access memory device, an insulating layer covering an upper portion of a conductive layer may be provided with an ozone gas so as to change the property of the upper portion of the insulating layer. The upper portion of the insulating layer may be chemically removed to expose the upper portion of the conductive layer. The exposed upper portion of the conductive layer may be removed so as to transform the conductive layer into a lower electrode. The remaining portion of the insulating layer may be removed, and an upper electrode may be formed on the lower electrode.Type: ApplicationFiled: September 14, 2007Publication date: March 20, 2008Inventors: Kwang-Sub Yoon, Jung-Hyeon Lee, Bong-Cheol Kim, Se-Young Park