Patents by Inventor Jung Hyeong Kim

Jung Hyeong Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12254953
    Abstract: A calibration device is coupled to a communication line shared by plural devices. The calibration device is configured to perform an iterative eye width scanning by adjusting a set voltage level by a preset level from a first voltage level to a reference center voltage level, wherein the first voltage level corresponds to a cross point where values of signals or data, which are transmitted via the communication lines, are changed in different directions; and determine, as a zero crossing for the signals or the data, a voltage level corresponding to a largest value among a plurality of eye widths obtained through the iterative eye width scanning.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: March 18, 2025
    Assignee: SK hynix Inc.
    Inventors: In Seok Kong, Chan Keun Kwon, Hee Jun Kim, Sung Ah Lee, Jung Hwan Lee, Jun Seo Jang, Jae Hyeong Hong
  • Publication number: 20250062929
    Abstract: A method for performing sidelink groupcast transmission by a transmission terminal includes the steps of: classifying reception terminals belonging to a subject group into two or more subgroups; allocating different groupcast feedback schemes to the two or more subgroups; performing groupcast transmission to the reception terminals; and receiving feedback information from terminals belonging to at least one subgroup among the two or more subgroups according to the different groupcast feedback schemes.
    Type: Application
    Filed: November 5, 2024
    Publication date: February 20, 2025
    Inventors: Jung Hoon LEE, Ju Ho PARK, Jun Hwan LEE, Il Gyu KIM, Jun Hyeong KIM, Go San NOH, Hee Sang CHUNG
  • Publication number: 20250062424
    Abstract: Discussed is a battery movement detection apparatus that may include a speed sensor configured to obtain speed information of a tray accommodating a battery, a power supply unit configured to provide a driving power, an environment sensor configured to obtain environment information about a surrounding environment of the battery movement detection apparatus, a communication unit configured to transmit the speed information to a battery position detection apparatus, and a controller configured to calculate an available limit of the power supply unit based on the environment information and control an operation of the communication unit based on the available limit of the power supply unit.
    Type: Application
    Filed: November 2, 2022
    Publication date: February 20, 2025
    Applicant: LG ENERGY SOLUTION, LTD.
    Inventors: Hu Jun LEE, Sang Hoon LEE, Moon Koo CHUNG, Jung Hoon LEE, Jung Hyun KWON, Duk You KIM, Seok Hyeong HAM
  • Publication number: 20250057024
    Abstract: A display device including: a substrate; a first electrode on the substrate; a pixel defining layer having a pixel opening, wherein the first electrode is in the pixel opening; a light emitting layer in the pixel opening; a second electrode on the light emitting layer and the pixel defining layer; an encapsulation layer on the second electrode; a first sensing electrode part on the encapsulation layer; a first sensing insulating layer on the first sensing electrode part; a second sensing electrode part and a reflective layer positioned on the first sensing insulating layer; and a first light blocking layer and a second light blocking layer on the first sensing insulating layer; wherein at least a portion of a lower surface of the reflective layer is inclined.
    Type: Application
    Filed: February 28, 2024
    Publication date: February 13, 2025
    Inventors: Jin Hyeong LEE, Su Jeong KIM, Wooyoung KIM, Eunbee LEE, Jung-Woo LEE
  • Publication number: 20250039804
    Abstract: An operation method of an IAB node in a communication system may comprise: measuring a power difference between a first signal received from a first node and a second signal received from a second node; controlling a transmit power of each of the first node and the second node based on the power difference; generating scheduling information for allowing the first node and the second node to simultaneously transmit signals; transmitting the scheduling information to the first node and the second node; and receiving signals that the first node and the second node simultaneously transmit according to the scheduling information by using the transmit power.
    Type: Application
    Filed: October 16, 2024
    Publication date: January 30, 2025
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jun Hyeong KIM, Seon Ae KIM, IL GYU KIM, Go San NOH, Hee Sang CHUNG, Dae Soon CHO, Sung Woo CHOI, Seung Nam CHOI, Jung Pil CHOI
  • Patent number: 12014782
    Abstract: A memory device includes a memory block to which a plurality of lines are connected. The memory device also includes a plurality of memory cells respectively connected to word lines among the plurality of lines, wherein the plurality of memory cells are formed as a plurality of plug holes formed in a stack structure between a drain select line among the plurality of lines and a slit. The memory device further includes a plurality of page buffers connected to the plurality of memory cells through a plurality of bit lines among the plurality of lines. The memory device additionally includes a peripheral circuit for performing a read operation on the plurality of memory cells. The peripheral circuit includes a voltage generator configured to control a signal applied to the plurality of page buffers so that the read operation is performed according to positions of the plug holes.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: June 18, 2024
    Assignee: SK hynix Inc.
    Inventor: Jung Hyeong Kim
  • Publication number: 20240074186
    Abstract: A semiconductor device may include a gate structure including a first conductive layer, a second conductive layer, and a third conductive layer, the third conductive layer being disposed between the first conductive layer and the second conductive layer and thicker than the first conductive layer and the second conductive layer, channel structures passing through the gate structure, and an isolation structure including a first portion passing through the second conductive layer and extended into the channel structures and a second portion protruding from the first portion into the third conductive layer and disposed between the channel structures.
    Type: Application
    Filed: December 9, 2022
    Publication date: February 29, 2024
    Inventor: Jung Hyeong KIM
  • Publication number: 20230200067
    Abstract: Provided herein is a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a gate stacked body including interlayer insulating layers and conductive patterns that are alternately stacked in a vertical direction on a substrate, a channel structure penetrating at least a portion of the gate stacked body, and an upper surface of the channel structure left exposed by the gate stacked body.
    Type: Application
    Filed: April 27, 2022
    Publication date: June 22, 2023
    Applicant: SK hynix Inc.
    Inventor: Jung Hyeong Kim
  • Publication number: 20220392544
    Abstract: A memory device includes a memory block to which a plurality of lines are connected. The memory device also includes a plurality of memory cells respectively connected to word lines among the plurality of lines, wherein the plurality of memory cells are formed as a plurality of plug holes formed in a stack structure between a drain select line among the plurality of lines and a slit. The memory device further includes a plurality of page buffers connected to the plurality of memory cells through a plurality of bit lines among the plurality of lines. The memory device additionally includes a peripheral circuit for performing a read operation on the plurality of memory cells. The peripheral circuit includes a voltage generator configured to control a signal applied to the plurality of page buffers so that the read operation is performed according to positions of the plug holes.
    Type: Application
    Filed: December 23, 2021
    Publication date: December 8, 2022
    Applicant: SK hynix Inc.
    Inventor: Jung Hyeong KIM
  • Patent number: 9721670
    Abstract: A semiconductor device includes a plurality of first memory strings each first memory string having a channel with a first length and a plurality of second memory strings each second memory string having a channel with a second length shorter than the first length. A method of operating the semiconductor device includes: performing a first read operation on the first read unit, wherein the first read unit includes the first memory cells sharing the same first word line among first memory cells included in the plurality of the first memory strings; and performing a second read operation on the second read unit, wherein the second read unit includes the second memory cells sharing the same second word line among second memory cells included in the plurality of the second memory strings.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: August 1, 2017
    Assignee: SK Hynix Inc.
    Inventor: Jung Hyeong Kim