Abstract: A semiconductor system includes one or more core chips including a plurality of memory banks; one or more replacement storage units; and a base chip suitable for: first detecting a memory bank having an access frequency that satisfies a first condition, second detecting whether an utilization rate of the first detected memory bank satisfies a second condition, and replacing the second detected memory bank with one among the replacement storage units.

Abstract: A memory controller may be provided. The memory controller may include a wear-leveler may be configured to determine whether execution of a swapping operation is required based on reception of a write command for a stack region.

Abstract: An exemplary embodiment of the present disclosure provides a color conversion panel including: a substrate; a polarization layer that is disposed on the substrate and includes a plurality of polarization patterns spaced apart from each other at a predetermined interval; and a color conversion layer that is disposed on the polarization layer, wherein at least one of the plurality of polarization patterns may include an external light interference layer disposed on the substrate and a reflection layer disposed on the external light interference layer.

Abstract: A semiconductor device may be provided. The semiconductor device may include an error correction circuit and a verification operation control circuit. The error correction circuit may be configured to output first correction data obtained by correcting an error of first read data inputted through a transmission data signal received, externally from the error correction circuit, as a correction data signal and configured to generate a write control signal according to the number of errors of the first read data. The verification operation control circuit may be configured to receive first correction data through the correction data signal to output the first correction data through an internal correction data signal and configured to generate an internal command signal for storing the first correction data externally from the semiconductor device, based on the write control signal.

Abstract: A memory system includes: a plurality of memory devices, one of which includes an unrepaired defective memory cell; a control bus that is shared by the plurality of the memory devices; a plurality of data buses assigned to each of the plurality of the memory devices; and a memory controller that communicates with the plurality of the memory devices through the control bus and the plurality of the data buses, a control latency of the memory device including unrepaired defective memory cells is set differently from a control latency of the other memory devices, where the control latency is used for recognizing control signals of the control bus.

Abstract: In an embodiment of the present disclosure, a memory module may be provided. In an embodiment of the present disclosure, a system may be provided. In an embodiment of the present disclosure, an operation of a system and memory module may be provided. The memory module may include a plurality of ranks in which a defragmentation operation of a memory is performed based on entrance of a low-power operation mode, and a vacant region of the memory is powered off based on entrance of a self-refresh mode after the defragmentation operation is ended. The memory module may include a page table of which data are updated based on an ending of the defragmentation operation of the memory.

Abstract: A liquid crystal display including: a liquid crystal display including: a first polarizer, a second polarizer, a gate line, a data line, a thin film transistor, a pixel electrode, a first light blocking member, a second light blocking member, a liquid crystal layer, and a common electrode; a color conversion panel including a third light blocking member and a color conversion media layer, the color conversion panel being disposed on the liquid crystal panel; and a backlight assembly configured to supply light to the liquid crystal panel and the color conversion panel, wherein the first light blocking member overlaps the data line, wherein the second light blocking member is disposed between the first light blocking member and the third light blocking member, the third light blocking member overlapping the first light blocking member, and wherein the third light blocking member overlaps the second light blocking member.

Abstract: A memory module may include a first memory device configured to be controlled by a host memory controller, to transmit/receive data to/from the host memory controller in a first mode, and to transmit/receive data to/from a module memory controller in a second mode, a second memory device configured to be controlled by the module memory controller and to transmit/receive data to/from the module memory controller in the second mode, and the module memory controller configured to monitor control of the first memory device by the host memory controller, to exchange data such that the data is transmitted/received between the first memory device and the second memory device in the second mode, and to control the second memory device.

Abstract: A semiconductor system includes one or more core chips including a plurality of memory banks; one or more replacement storage units; and a base chip suitable for: first detecting a memory bank having an access frequency that satisfies a first condition, second detecting whether an utilization rate of the first detected memory bank satisfies a second condition, and replacing the second detected memory bank with one among the replacement storage units.

Abstract: A memory device may include: a data determination unit for receiving page data from a main memory device, and distinguishing between first and second data based on tag information of the page data; an index management unit for storing an index of the first data; a first cache for storing the second data, and writing back first victim data to the main memory device, the first victim data being selected when the first cache is full; and a second cache for storing the first victim data transferred from the first cache when a write count of the first victim data is smaller than a first threshold value, updating tag information of second victim data to a value indicating the first data, the second victim data being selected when the second cache is full, and storing the second victim data in the main memory device.

Abstract: A memory system includes: a non-volatile memory device including a normal region in which Most Significant Bits (MSBs) and Least Significant Bits (LSBs) stored in memory cells are accessed simultaneously, a hot region in which MSBs stored in memory cells are accessed, and a cold region in which LSBs stored in memory cells are accessed; and a memory controller controlling the non-volatile memory device, Herein, the memory controller includes: a read/write counter that counts the number of read operations and the number of write operations that are performed for each of logical cluster to thereby produce a counting result; and a region selector that maps each logical cluster to one among the normal region, the hot region and the cold region based on the counting result to thereby produce mapping data.

Abstract: A backlight assembly includes a first light source part including a plurality of first light sources configured to generate light having a first color and a plurality of second light sources configured to generate light having a second color different from the first color, and a light guiding plate including a first incident surface and an exiting surface adjacent to the first incident surface. The exiting surface is configured to allow the light to pass therethrough. The exiting surface includes a first peripheral portion configured to absorb the light having the second color and a central portion adjacent to the first peripheral portion and configured to allow the light to pass therethrough. The first and second light sources are alternately located.

Abstract: A semiconductor device may include a pattern detector configured to select any one of a plurality of stride patterns as a detect pattern by referring to an input address, and the pattern detector may be configured to generate a prefetch address. The semiconductor device may also include a prefetch controller configured to generate a prefetch request according to the prefetch address generated by the pattern detector. The semiconductor device may also include a first storage unit configured to store prefetch data provided from a memory device according to the prefetch request generated by the prefetch controller, and a second storage unit configured to store prefetch data removed from the first storage unit.

Abstract: A memory device may include one or more multi-channel memories and an interface unit suitable for interfacing the multi-channel memories. The interface unit may include a first data interface suitable for transferring data for the first channel of the multi-channel memories, a second data interface suitable for transferring data for the second channel of the multi-channel memories, and an extra data interface suitable for transferring data for a selected one of the first channel and the second channel so that the data is additionally transmitted.

Abstract: A color conversion panel includes a substrate, a plurality of color conversion layers and a transmission layer on the substrate, a capping layer on the plurality of color conversion layers and the transmission layer, and a filter layer on the capping layer.

Abstract: A memory system may include a memory module comprising a plurality of memory chips mounted therein each memory chip comprising a plurality of banks, the memory chips being simultaneously accessible based on the same command and address; and a memory controller suitable for mapping the banks of the memory chips to each other while rearranging an order of the banks of each of the memory chips based on repair information of the memory chips.

Abstract: A liquid crystal display according to an exemplary embodiment of the inventive concept includes a substrate; a thin film transistor positioned on the substrate; a pixel electrode connected to the thin film transistor; a roof layer positioned to face the pixel electrode; a liquid crystal layer positioned between the pixel electrode and the roof layer within a plurality of microcavities; a capping layer positioned adjacent to the microcavities; and a color conversion panel including a plurality of color conversion media layers on the roof layer and the capping layer, wherein the capping layer is positioned along a trench formed between the plurality of microcavities.

Abstract: A backlight assembly includes a plurality of first light sources configured to emit a first color, and a plurality of second light sources configured to emit a second color different from the first color, where the backlight assembly is divided in a first boundary area, a second boundary area spaced apart from the first boundary area in a first direction, and a middle area between the first boundary area and the second boundary area, and an arrangement direction of first and second light sources of the plurality of first and second light sources in the first and second boundary areas is different from an arrangement direction of first and second light sources of the plurality of first and second light sources in the middle area.

Abstract: A liquid crystal display including: a liquid crystal display including: a first polarizer, a second polarizer, a gate line, a data line, a thin film transistor, a pixel electrode, a first light blocking member, a second light blocking member, a liquid crystal layer, and a common electrode; a color conversion panel including a third light blocking member and a color conversion media layer, the color conversion panel being disposed on the liquid crystal panel; and a backlight assembly configured to supply light to the liquid crystal panel and the color conversion panel, wherein the first light blocking member overlaps the data line, wherein the second light blocking member is disposed between the first light blocking member and the third light blocking member, the third light blocking member overlapping the first light blocking member, and wherein the third light blocking member overlaps the second light blocking member.

Abstract: A display apparatus includes a display panel, a display panel driver, a light source part and a local dimming driver. The display panel includes a first subpixel having a first primary color, a second subpixel having a second primary color and a transparent subpixel. The display panel driver is configured to set grayscales of the first subpixel, the second subpixel and the transparent subpixel. The light source part includes a plurality of light emitting blocks configured to provide light to the display panel. The light emitting block includes a first light source configured to generate a light of a mixed color and a second light source configured to generate a light of a third primary color. The local dimming driver is configured to alternately turn on and off the first light source and the second light source and configured to independently drive the light emitting blocks.