Patents by Inventor Jung-Hyun Roh

Jung-Hyun Roh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955531
    Abstract: An integrated circuit device includes a fin-type active region protruding from a top surface of a substrate and extending in a first direction parallel to the top surface of the substrate, a gate structure intersecting with the fin-type active region and extending on the substrate in a second direction perpendicular to the first direction, a source/drain region on a first side of the gate structure, a first contact structure on the source/drain region, and a contact capping layer on the first contact structure. A top surface of the first contact structure has a first width in the first direction, a bottom surface of the contact capping layer has a second width greater than the first width stated above in the first direction, and the contact capping layer includes a protruding portion extending outward from a sidewall of the first contact structure.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: April 9, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-young Kwak, Ji-ye Kim, Jung-hwan Chun, Min-chan Gwak, Dong-hyun Roh, Jin-wook Lee, Sang-jin Hyun
  • Patent number: 10720396
    Abstract: A semiconductor chip including a substrate including a plurality of chip areas and a line-shaped scribe area defining the chip areas, an integrated circuit (IC) structure on the chip area, the IC structure including a plurality of transistors and a plurality of stacked wiring structures connected to the transistors, and a warpage protector in the line-shaped scribe area and corresponding to the stacked wiring structures, the warpage protector supporting at least one side of the IC structure may be provided.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: July 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jung-Hyun Roh
  • Patent number: 10629546
    Abstract: A semiconductor device including a substrate including a central region and a peripheral region surrounding the central region, a semiconductor integrated circuit in the central region, and a three-dimensional crack detection structure in the peripheral region, the three-dimensional crack detection structure surrounding the central region, the three-dimensional crack detection structure including a first pattern, a second pattern, and a third pattern, the first and second patterns extending in a first direction and spaced apart from each other, the third pattern being parallel to an upper surface of the substrate and connecting the first and second patterns to each other, the third pattern including a first portion and a second portion, the first and second portions extending in a second direction and a third direction respectively, the second direction intersecting with the first direction, the third direction intersecting with the first and second directions may be provided.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: April 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jung Hyun Roh
  • Publication number: 20190235017
    Abstract: A semiconductor device including a substrate including a central region and a peripheral region surrounding the central region, a semiconductor integrated circuit in the central region, and a three-dimensional crack detection structure in the peripheral region, the three-dimensional crack detection structure surrounding the central region, the three-dimensional crack detection structure including a first pattern, a second pattern, and a third pattern, the first and second patterns extending in a first direction and spaced apart from each other, the third pattern being parallel to an upper surface of the substrate and connecting the first and second patterns to each other, the third pattern including a first portion and a second portion, the first and second portions extending in a second direction and a third direction respectively, the second direction intersecting with the first direction, the third direction intersecting with the first and second directions may be provided.
    Type: Application
    Filed: August 27, 2018
    Publication date: August 1, 2019
    Applicant: Samsung Electronics Co., Ltd
    Inventor: Jung Hyun ROH
  • Publication number: 20190164910
    Abstract: A semiconductor chip including a substrate including a plurality of chip areas and a line-shaped scribe area defining the chip areas, an integrated circuit (IC) structure on the chip area, the IC structure including a plurality of transistors and a plurality of stacked wiring structures connected to the transistors, and a warpage protector in the line-shaped scribe area and corresponding to the stacked wiring structures, the warpage protector supporting at least one side of the IC structure may be provided.
    Type: Application
    Filed: September 10, 2018
    Publication date: May 30, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Jung-Hyun Roh
  • Publication number: 20110124273
    Abstract: In a wafer polishing apparatus, the height of the wheel tip can be adjusted. The wafer polishing apparatus includes a wheel tip constructed and arranged to be in direct contact with a wafer; a spindle shaft configured to receive power to enable rotation of the wheel tip; a wheel shank positioned at a lower part of the spindle shaft and supporting the wheel tip, the wheel tip not being directly fixed thereto; and a moving shaft having a first side on which the wheel tip is mounted and an opposite side to which the spindle shaft is connected, and relatively movable with respect to the spindle shaft.
    Type: Application
    Filed: May 27, 2010
    Publication date: May 26, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Hyun Roh, Heui-Seog Kim, Wha-Su Sin, Jun-Soo Han