Patents by Inventor Jung II Cho

Jung II Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070232019
    Abstract: A method for forming an isolation structure in a nonvolatile memory device includes forming a gate insulation layer, a gate conductive layer, and a hard mask over a substrate, etching the hard mask, the gate conductive layer, the gate insulation layer, and a portion of the substrate to form a trench, forming a first insulation layer over an inner surface of the trench and filled in a portion of the trench, removing the hard mask, and forming a second insulation layer over the first insulation layer and filled in the trench.
    Type: Application
    Filed: December 28, 2006
    Publication date: October 4, 2007
    Inventor: Jung-II Cho
  • Publication number: 20070128797
    Abstract: A flash memory device and a method for fabricating the same are provided. The method includes: preparing a semi-finished substrate where floating gates and an isolation layer isolating the floating gates are formed; recessing a predetermined portion of the isolation layer to make the floating gates protrude; etching another predetermined portion of the isolation layer to form a trench therein; forming a dielectric layer over the isolation layer and the floating gates; and forming a control gate over the dielectric layer such that the control gate fills the trench.
    Type: Application
    Filed: June 27, 2006
    Publication date: June 7, 2007
    Inventor: Jung-II Cho
  • Patent number: 6465293
    Abstract: A method of manufacturing a flash memory cell is disclosed. The method comprises the steps of forming an oxide film on a semiconductor substrate in which a device separation film is formed and then patterning the oxide film to expose the semiconductor substrate at a portion in which a floating gate will be formed; sequentially forming a tunnel oxide film and a first polysilicon layer on the entire structure, and then flattening the first polysilicon layer until the tunnel oxide film is exposed to form a floating gate; etching the tunnel oxide film and the oxide film in the exposed portion to a given thickness and the forming a dielectric film on the entire structure; sequentially forming a second polysilicon layer, a tungsten silicide layer and a hard mask and then patterning them to form a control gate; and injecting impurity ions into the semiconductor substrate at the both sides of the floating gate to form a junction region.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: October 15, 2002
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Soo Young Park, Jung II Cho