Abstract: An array substrate for a liquid crystal display device, comprises: a substrate having a display region and a non-display region; a gate line and first and second data lines on the substrate; first and second thin film transistors in the first and second pixel regions, respectively, the first thin film transistor connected to the gate line and the first data line, the second thin film transistor connected to the gate line and the second data line; a planarization layer on the first and second thin film transistors, the planarization layer having a drain contact hole exposing both of drain electrodes of the first and second thin film transistors; and a pixel electrode and a common electrode over the planarization layer.

Abstract: A liquid crystal display device is provided. The liquid crystal display device includes a gate line and a data line formed on a substrate; a thin film transistor formed at an intersection of the gate line and the data line; a pixel electrode connected to the thin film transistor; a common electrode substantially parallel to the pixel electrode; and a conductive pattern in contact with the common electrode at a lateral side surface of the common electrode.

Abstract: The present invention relates to the elucidation of a gene that can act as a novel marker for liver cancer diagnosis and to diagnostic and prognostic measurements of liver cancer using the same. More specifically, it relates to a diagnosis kit that enables diagnostic and prognostic measurement of a liver cancer using a preparation that measures expression levels of at least one gene selected from a group of liver cancer diagnosis markers consisting of S100P, NK4, CCL20, CSPG2, PLAU, MMP12, ESM-1, ABHD7, HCAPG, CXCL-3, Col5A2, MAGEA, GSN, CDC2, CST1, MELK, ATAD2, FAP and MSN and/or a method for diagnostic and prognostic measurement of liver cancer using the same. These have been discovered using normal liver tissues and liver cancer tissues collected from the same liver cancer patient of the present invention and represent the markers whose accuracy and reliability have been greatly improved as markers of liver cancer.

Abstract: A liquid crystal display device includes first and second substrates facing each other, wherein a pixel region is defined on the first and second substrates, first and second grooves formed on an inner surface of the first substrate, a gate line formed in the first groove along a direction, a common line formed in the second groove and parallel to the gate line, a data line crossing the gate line to define the pixel region, a thin film transistor connected to the gate line and the data line, and a light-shielding pattern of a black inorganic material and around the gate line, the data line and the common line.

Abstract: An array substrate for a transflective liquid crystal display device includes: a substrate; a gate line and a data line on the substrate, the gate line and the data line crossing each other to define a pixel region including a transmissive area and a reflective area surrounding the transmissive area; a thin film transistor having a gate insulating layer, the thin film transistor electrically connected to the gate line and the data line; a first passivation layer having a drain contact hole exposing a drain electrode of the thin film transistor and a through hole exposing the substrate in the transmissive area; a pixel electrode on the first passivation layer, the pixel electrode contacting the substrate in the transmissive area through the through hole; and a reflective plate on the pixel electrode, the reflective plate being electrically connected to the drain electrode through the drain contact hole and to the pixel electrode.

Abstract: An array substrate for a transflective liquid crystal display device includes: a substrate; a gate line and a data line on the substrate, the gate line and the data line crossing each other to define a pixel region including a transmissive area and a reflective area surrounding the transmissive area; a thin film transistor having a gate insulating layer, the thin film transistor connected to the gate line and the data line; a first passivation layer on the thin film transistor, the first passivation layer having a drain contact hole exposing a drain electrode of the thin film transistor and a through hole exposing the substrate in the transmissive area; a reflective plate on the first passivation layer; a second passivation layer on the reflective plate; and a pixel electrode on the second passivation layer, the pixel electrode contacting the substrate in the transmissive area through the through hole and contacting the drain electrode through the drain contact hole.

Abstract: The present invention relates to an exposing device which can form a micron pattern even with an exposing device having a low resolving power by changing a mask pattern, methods for forming a pattern, a channel, and a hole respectively, and a liquid crystal display device therewith and a method for fabricating the same.

Abstract: A MOS transistor having a T-shaped gate electrode and a method for fabricating the same are provided, wherein the MOS transistor includes a T-shaped gate electrode on a semiconductor substrate; an L-shaped lower spacer disposed at both sides of the gate electrode to cover a top surface of the semiconductor substrate; and low-, mid-, and high-concentration impurity regions formed in the semiconductor substrate of both sides of the gate electrode. The high-concentration impurity region is disposed in the semiconductor substrate next to the lower spacer and the mid-concentration impurity region is disposed between the high- and low-concentration impurity regions. A MOS transistor according to the present invention provides a decrease in a capacitance, a decrease in a channel length, and an increase in a cross-sectional area of the gate electrode. At the same time, the mid-concentration impurity region provides a decrease in a source/drain resistance Rsd.

Abstract: A semiconductor device includes a hetero grain stack gate (HGSG). The device includes a semiconductor substrate having a surface, a gate insulating layer formed over the surface of the semiconductor substrate, and a gate electrode formed over the gate insulating layer, wherein the gate electrode includes a lower poly-SiGe layer having a columnar crystalline structure, and an upper poly-Si layer having a random crystalline structure. In one embodiment, the gate electrode includes a lower poly-SiGe layer having a columnar crystalline structure, an intermediate layer having an random crystalline structure, and an upper poly-Si layer having a columnar crystalline structure.

Abstract: A semiconductor device includes a hetero grain stack gate (HGSG). The device includes a semiconductor substrate having a surface, a gate insulating layer formed over the surface of the semiconductor substrate, and a gate electrode formed over the gate insulating layer, wherein the gate electrode includes a lower poly-SiGe layer having a columnar crystalline structure, and an upper poly-Si layer having a random crystalline structure. In one embodiment, the gate electrode includes a lower poly-SiGe layer having a columnar crystalline structure, an intermediate layer having an random crystalline structure, and an upper poly-Si layer having a columnar crystalline structure.

Abstract: A trench isolation structure and method of forming the trench isolation structure, in which a recess-preventing insulator layer is formed at least between a pad nitride layer and a trench-burying insulator layer. In the method and resulting structure, the etch resistivity of the recess-preventing insulator layer is higher than that of the trench-burying insulator layer. Therefore, the etch rate of the recess-preventing insulator layer is lower than that of the trench-burying insulator layer.