Patents by Inventor Jung-Il MOK

Jung-Il MOK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory core and semiconductor memory device including the same
    Patent number: 9159398
    Abstract: A semiconductor device may include a first memory cell connected to a bit-line and a first word-line, a second memory cell connected to a complementary bit-line and a second word-line, and an equalizer. The equalizer may be configured to transition a voltage of the bit-line and the complementary bit-line from a first voltage to a second voltage different from the first voltage at a first time period when the bit-line and complementary bit line are floating, and to transition the voltage of at least one of the bit-line and the complementary bit-line from the second voltage to a third voltage at a second time period after the first time period when the bit-line and complementary bit line are floating, the third voltage being different from the first and second voltages.
    Type: Grant
    Filed: January 5, 2014
    Date of Patent: October 13, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Il Mok, Jong-Hyoung Lim, Dae-Sun Kim, Ji-Hyun Lee
  • MEMORY CORE AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME
    Publication number: 20140198589
    Abstract: A semiconductor device may include a first memory cell connected to a bit-line and a first word-line, a second memory cell connected to a complementary bit-line and a second word-line, and an equalizer. The equalizer may be configured to transition a voltage of the bit-line and the complementary bit-line from a first voltage to a second voltage different from the first voltage at a first time period when the bit-line and complementary bit line are floating, and to transition the voltage of at least one of the bit-line and the complementary bit-line from the second voltage to a third voltage at a second time period after the first time period when the bit-line and complementary bit line are floating, the third voltage being different from the first and second voltages.
    Type: Application
    Filed: January 5, 2014
    Publication date: July 17, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jung-Il MOK, Jong-Hyoung LIM, Dae-Sun KIM, Ji-Hyun LEE