Abstract: In a non-volatile memory system, a plurality of main memory cells for storing data is arranged in a data cell array and a plurality of reference memory cells is arranged in a reference cell array. The reference cell array includes first reference word lines connected to first reference memory cells and extending, second reference word lines connected to second reference memory cells and extending alternately with the first reference word lines, reference bit lines to which the first and the second reference memory cells are alternately connected in a line and a combined cell having a pair of the first and second reference memory cells and generating a reference signal for processing the data. The first and the second reference memory cells have different cell characteristics. The stability of the reference signal is improved irrespective of the differentiation of the first and the second reference memory cells.

Abstract: A flat panel display device includes a display module, a protection window member and a layer disposed in an area between the protection window member and a display area of the display module. The protection window member includes a stepped portion within which the layer is disposed. The stepped portion may include a recess or a plurality of layers.

Abstract: In a non-volatile memory system, a plurality of main memory cells for storing data is arranged in a data cell array and a plurality of reference memory cells is arranged in a reference cell array. The reference cell array includes first reference word lines connected to first reference memory cells and extending, second reference word lines connected to second reference memory cells and extending alternately with the first reference word lines, reference bit lines to which the first and the second reference memory cells are alternately connected in a line and a combined cell having a pair of the first and second reference memory cells and generating a reference signal for processing the data. The first and the second reference memory cells have different cell characteristics. The stability of the reference signal is improved irrespective of the differentiation of the first and the second reference memory cells.

Abstract: A non-volatile memory device includes memory cell active regions and common source active regions extending in parallel on a semiconductor substrate, a self aligned source active region disposed on the semiconductor substrate that intersects the memory cell active regions and the common source active regions and connects the memory cell active regions to the common source active regions, word lines disposed on the memory cell active regions and the common source active regions that intersect the memory cell active regions and the common source active regions, and memory cell transistors formed by the intersection of the word lines and the memory cell active regions, and common source line transistors formed by the intersection of the word lines and the common source active regions, wherein source and drain regions of each of the common source line transistors are separated from each other in the semiconductor substrate.

Abstract: Methods of searching for a sync word in an MPEG compressed audio bitstream including a plurality of MPEG audio frames can include determining whether first data in the bitstream has a value equal to a sync word value. It can be determined whether the first data is a valid sync word based on a comparison of a plurality of data that are separated in the bitstream from the first data by at least a frame length to the sync word value.

Abstract: A flat panel display device includes a display module, a protection window member and a layer disposed in an area between the protection window member and a display area of the display module. The protection window member includes a stepped portion within which the layer is disposed. The stepped portion may include a recess or a plurality of layers.

Abstract: Methods for erasing an integrated circuit memory device having a cell array region that includes a main cell array region, a first dummy cell array region on a first side of the main cell array region and a second dummy cell array region on a second side of the main cell array region are provided. A first erasure voltage is applied to a plurality of main control gate electrodes in the main cell array region. The plurality of main control gate electrodes include a first outermost main control gate electrode adjacent to the first dummy cell array region and a second outermost main control gate electrode adjacent to the second dummy cell array region. A second erasure voltage is applied to an integrated circuit substrate in the main cell array region. The second erasure voltage is greater than the first erasure voltage.

Abstract: Selective erase method for a flash memory device including a group of memory cells arranged in rows and columns include performing an erase operation on the group of memory cells and verifying the erase operation on the group of memory cells to determine threshold voltages of the memory cells. At least one row of memory cells including memory cells having a threshold voltage lower than a desired erase threshold voltage is identified. A further erase operation is performed on the group of memory cells excluding memory cells of the at least one row of memory cells including memory cells having a threshold voltage lower than a desired erase threshold voltage.

Abstract: Methods for erasing an integrated circuit memory device having a cell array region that includes a main cell array region, a first dummy cell array region on a first side of the main cell array region and a second dummy cell array region on a second side of the main cell array region are provided. A first erasure voltage is applied to a plurality of main control gate electrodes in the main cell array region. The plurality of main control gate electrodes include a first outermost main control gate electrode adjacent to the first dummy cell array region and a second outermost main control gate electrode adjacent to the second dummy cell array region. A second erasure voltage is applied to an integrated circuit substrate in the main cell array region. The second erasure voltage is greater than the first erasure voltage.

Abstract: Methods for erasing an integrated circuit memory device having a cell array region that includes a main cell array region, a first dummy cell array region on a first side of the main cell array region and a second dummy cell array region on a second side of the main cell array region are provided. A first erasure voltage is applied to a plurality of main control gate electrodes in the main cell array region. The plurality of main control gate electrodes include a first outermost main control gate electrode adjacent to the first dummy cell array region and a second outermost main control gate electrode adjacent to the second dummy cell array region. A second erasure voltage is applied to an integrated circuit substrate in the main cell array region. The second erasure voltage is greater than the first erasure voltage.

Abstract: Selective erase method for a flash memory device including a group of memory cells arranged in rows and columns include performing an erase operation on the group of memory cells and verifying the erase operation on the group of memory cells to determine threshold voltages of the memory cells. At least one row of memory cells including memory cells having a threshold voltage lower than a desired erase threshold voltage is identified. A further erase operation is performed on the group of memory cells excluding memory cells of the at least one row of memory cells including memory cells having a threshold voltage lower than a desired erase threshold voltage.

Abstract: Methods of searching for a sync word in an MPEG compressed audio bitstream including a plurality of MPEG audio frames can include determining whether first data in the bitstream has a value equal to a sync word value. It can be determined whether the first data is a valid sync word based on a comparison of a plurality of data that are separated in the bitstream from the first data by at least a frame length to the sync word value.

Abstract: Methods for erasing an integrated circuit memory device having a cell array region that includes a main cell array region, a first dummy cell array region on a first side of the main cell array region and a second dummy cell array region on a second side of the main cell array region are provided. A first erasure voltage is applied to a plurality of main control gate electrodes in the main cell array region. The plurality of main control gate electrodes include a first outermost main control gate electrode adjacent to the first dummy cell array region and a second outermost main control gate electrode adjacent to the second dummy cell array region. A second erasure voltage is applied to an integrated circuit substrate in the main cell array region. The second erasure voltage is greater than the first erasure voltage.