Abstract: Semiconductor devices and methods of fabrication. A device includes a semiconductor substrate, a gate electrode insulated from the semiconductor substrate by a gate insulation layer, LDD-type source/drain regions formed at both sides of the gate electrode, an interlayer insulation layer formed over the gate electrode and the substrate, and a shared contact piercing the interlayer insulation layer and contacting the gate electrode and one of the LDD-type source/drain regions including at least a part of a lightly doped drain region. Multiple-layer spacers are formed on both sides of the gate structure and used as a mask in forming the LDD-type regions. At least one layer of the spacer is removed in the contact opening to widen the opening to receive a contact plug.

Abstract: Semiconductor devices and methods of fabrication. A device includes a semiconductor substrate, a gate electrode insulated from the semiconductor substrate by a gate insulation layer, LDD-type source/drain regions formed at both sides of the gate electrode, an interlayer insulation layer formed over the gate electrode and the substrate, and a shared contact piercing the interlayer insulation layer and contacting the gate electrode and one of the LDD-type source/drain regions including at least a part of a lightly doped drain region. Multiple-layer spacers are formed on both sides of the gate structure and used as a mask in forming the LDD-type regions. At least one layer of the spacer is removed in the contact opening to widen the opening to receive a contact plug.

Abstract: Semiconductor devices and methods of fabrication. A device includes a semiconductor substrate, a gate electrode insulated from the semiconductor substrate by a gate insulation layer, LDD-type source/drain regions formed at both sides of the gate electrode, an interlayer insulation layer formed over the gate electrode and the substrate, and a shared contact piercing the interlayer insulation layer and contacting the gate electrode and one of the LDD-type source/drain regions including at least a part of a lightly doped drain region. Multiple-layer spacers are formed on both sides of the gate structure and used as a mask in forming the LDD-type regions. At least one layer of the spacer is removed in the contact opening to widen the opening to receive a contact plug.

Abstract: A method of forming a trench isolation in a semiconductor substrate is described, which comprises the steps of forming a trench on the substrate, forming a diffusion barrier insulating layer, forming a thermal oxide layer both sidewall and bottom of the trench contacted with the diffusion barrier insulating layer, forming a nitride liner, and forming trench isolation material to fill the trench. A multi-structure of the barrier layer and the thermal oxide layer is provided between the nitride liner and the trench, resulting in minimization of transistor characteristic deterioration. A thin thermal oxide layer is formed to achieve improved trench etching profile.

Abstract: Methods of forming high-density contacts are provided. An interlayer insulating layer and an auxiliary layer having interconnection line patterns are sequentially formed on a substrate in which a conductive region is formed. Next, a contact photoresist pattern having a bar-shaped pattern is formed on the auxiliary layer. The bar-shaped pattern is substantially orthogonal to the interconnection line pattern formed in the auxiliary layer. Then, the interlayer insulating layer is etched at a contact region using the contact photoresist pattern and the auxiliary layer having the interconnection line pattern therein as an etching mask. Subsequently, the interlayer insulating layer is etched using the auxiliary layer having the interconnection line pattern as an etching mask to form a contact hole that extends through the interlayer insulating layer to the conductive region and to form an interconnection groove in an upper portion of the interlayer insulating layer.

Abstract: Semiconductor devices and methods of fabrication. A device includes a semiconductor substrate, a gate electrode insulated from the semiconductor substrate by a gate insulation layer, LDD-type source/drain regions formed at both sides of the gate electrode, an interlayer insulation layer formed over the gate electrode and the substrate, and a shared contact piercing the interlayer insulation layer and contacting the gate electrode and one of the LDD-type source/drain regions including at least a part of a lightly doped drain region. Multiple-layer spacers are formed on both sides of the gate structure and used as a mask in forming the LDD-type regions. At least one layer of the spacer is removed in the contact opening to widen the opening to receive a contact plug.

Abstract: A method of forming a trench isolation in a semiconductor substrate is described, which comprises the steps of forming a trench on the substrate, forming a diffusion barrier insulating layer, forming a thermal oxide layer both sidewall and bottom of the trench contacted with the diffusion barrier insulating layer, forming a nitride liner, and forming trench isolation material to fill the trench. A multi-structure of the barrier layer and the thermal oxide layer is provided between the nitride liner and the trench, resulting in minimization of transistor characteristic deterioration. A thin thermal oxide layer is formed to achieve improved trench etching profile.

Abstract: Methods of forming high-density contacts are provided. An interlayer insulating layer and an auxiliary layer having interconnection line patterns are sequentially formed on a substrate in which a conductive region is formed. Next, a contact photoresist pattern having a bar-shaped pattern is formed on the auxiliary layer. The bar-shaped pattern is substantially orthogonal to the interconnection line pattern formed in the auxiliary layer. Then, the interlayer insulating layer is etched at a contact region using the contact photoresist pattern and the auxiliary layer having the interconnection line pattern therein as an etching mask. Subsequently, the interlayer insulating layer is etched using the auxiliary layer having the interconnection line pattern as an etching mask to form a contact hole that extends through the interlayer insulating layer to the conductive region and to form an interconnection groove in an upper portion of the interlayer insulating layer.

Abstract: A process for forming a barrier metal layer and a metal layer on the surface of a contact hole formed on a semiconductor substrate. A titanium and a first titanium nitride layers are sequentially deposited on the surface of the contact hole and annealed, and thereafter, a second titanium nitride layer is deposited on the first titanium nitride layer and annealed, to thereby form a barrier metal layer. A first aluminum layer alloyed with silicon and copper of a given quantity, and a second aluminum layer alloyed with copper of a given quantity, are sequentially deposited on the barrier metal layer, and thereafter performed, the annealing process is performed. A third aluminum layer alloyed with copper of a given quantity is deposited on the second aluminum layer and annealed, to thereby form a metal layer.

Abstract: A method for forming a multilayer wiring, in a method for manufacturing a semiconductor device, is disclosed. The method comprises: forming a contact hole 33 on the surface of a conductive layer 29 by a photolithography, removing a photoresist by using plasma ashing at a predetermined temperature, pressure and amount of oxygen per unit cubic, and simultaneously forming a protective layer 35 consisting of a oxide layer on the surface of the exposed conductive layer. Thus, damage of the surface of wiring caused by the chemical reaction of an organic solvent and water in the subsequent process thereof, is prevented, to provide high density and high speed semiconductor integrated circuit whose electrode characteristics between two wiring layers is improved.

Abstract: This invention provides a method for manufacturing a semiconductor device which prevents residues from remaining around an etching pattern of a poly-silicon by making the poly-silicon be gradiently etched out. An oxide barrier layer is deposited over a poly-silicon layer, and impurities are implanted through the oxide barrier layer, wherein the concentration difference of impurities makes the poly-silicon have a graded sidewalls, and the value of resistance is controlled by the quantity of impurities. After removing the oxide barrier layer the poly-silicon is selectively etched into a poly electrode having a graded sidewall. The thermal treatment of the poly electrode is carried out and a polysilicon for another electrode is deposited and etched out.