Patents by Inventor Jung-Jen Chen
Jung-Jen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240140900Abstract: A method for manufacturing methyltetrahydrophthalic anhydride is provided, which includes steps as follows. Maleic anhydride is added into a reactor. Piperylene is added into the reactor, so that the piperylene and the maleic anhydride undergo a first addition reaction. When a conversion rate of the maleic anhydride is more than 25%, the first addition reaction is completed. Isoprene is added into the reactor, so that the isoprene and the maleic anhydride undergo a second addition reaction to obtain a methyltetrahydrophthalic anhydride product. The methyltetrahydrophthalic anhydride product contains 3-methyltetrahydrophthalic anhydride and 4-methyltetrahydrophthalic anhydride.Type: ApplicationFiled: December 21, 2022Publication date: May 2, 2024Inventors: TE-CHAO LIAO, JUNG-JEN CHUANG, CHUNG-YU CHEN, JUNG-TSU WU
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Publication number: 20240140925Abstract: A method for manufacturing a low-viscosity hardener is provided. The method includes the followings steps: providing a hardener crude product; and subjecting the hardener crude product and an alkaline catalyst to an isomerization reaction, so as to obtain the low-viscosity hardener. The hardener crude product contains 3-methyltetrahydrophthalic anhydride and 4-methyltetrahydrophthalic anhydride, and a weight ratio of the 3-methyltetrahydrophthalic anhydride to the 4-methyltetrahydrophthalic anhydride ranges from 7:3 to 3:7. A viscosity of the low-viscosity hardener ranges from 30 cps to 50 cps.Type: ApplicationFiled: January 11, 2023Publication date: May 2, 2024Inventors: TE-CHAO LIAO, JUNG-JEN CHUANG, CHUNG-YU CHEN, JUNG-TSU WU
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Publication number: 20240097403Abstract: A laser device is provided. The laser device includes a stack of epitaxial layers, a first conductive layer, an intermediate layer, and a first electrode. The stack of epitaxial layers has a central region and an edge region. The stack of epitaxial layers includes a first reflective structure, an active region disposed on the first reflective structure, a second reflective structure disposed on the active region. The first conductive layer disposes on the stack of epitaxial layers and covers the central region and at least a part of the edge region. The intermediate layer has a first opening that corresponding to the central region of the stack of epitaxial layers, wherein the intermediate layer comprises insulating material or metal. The first electrode disposes on the first conductive layer.Type: ApplicationFiled: September 14, 2023Publication date: March 21, 2024Inventors: Jung-Jen Li, Ching-En Huang, Hao-Ming Ku, Shih-I Chen
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Patent number: 11854901Abstract: A device is manufactured by providing a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.Type: GrantFiled: June 17, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Hsiung Yen, Ta-Chun Ma, Chien-Chang Su, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen
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Publication number: 20230383435Abstract: In an embodiment, an apparatus includes a first pyrometer and a second pyrometer configured to monitor thermal radiation from a first point and a second point on a backside of a wafer, respectively, a first heating source in a first region and a second heating source in a second region of an epitaxial growth chamber, respectively, where a first controller adjusts an output of the first heating source and the second heating source based upon the monitored thermal radiation from the first point and the second point, respectively, a third pyrometer and a fourth pyrometer configured to monitor thermal radiation from a third point and a fourth point on a frontside of the wafer, respectively, where a second controller adjusts a flow rate of one or more precursors injected into the epitaxial growth chamber based upon the monitored thermal radiation from the first, second, third, and fourth points.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Li-Ting Wang, Jung-Jen Chen, Ming-Hua Yu, Yee-Chia Yeo
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Publication number: 20230017768Abstract: In an embodiment, an apparatus includes a first pyrometer and a second pyrometer configured to monitor thermal radiation from a first point and a second point on a backside of a wafer, respectively, a first heating source in a first region and a second heating source in a second region of an epitaxial growth chamber, respectively, where a first controller adjusts an output of the first heating source and the second heating source based upon the monitored thermal radiation from the first point and the second point, respectively, a third pyrometer and a fourth pyrometer configured to monitor thermal radiation from a third point and a fourth point on a frontside of the wafer, respectively, where a second controller adjusts a flow rate of one or more precursors injected into the epitaxial growth chamber based upon the monitored thermal radiation from the first, second, third, and fourth points.Type: ApplicationFiled: July 16, 2021Publication date: January 19, 2023Inventors: Li-Ting Wang, Jung-Jen Chen, Ming-Hua Yu, Yee-Chia Yeo
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Publication number: 20220367690Abstract: In an embodiment, a device includes: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region including silicon; a second semiconductor region on the first semiconductor region, the second semiconductor region including silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack.Type: ApplicationFiled: July 20, 2022Publication date: November 17, 2022Inventors: Ji-Yin Tsai, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen, Yee-Chia Yeo
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Publication number: 20220328358Abstract: A device is manufactured by providing a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.Type: ApplicationFiled: June 17, 2022Publication date: October 13, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Hsiung Yen, Ta-Chun Ma, Chien-Chang Su, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen
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Patent number: 11437497Abstract: In an embodiment, a device includes: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region including silicon; a second semiconductor region on the first semiconductor region, the second semiconductor region including silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack.Type: GrantFiled: April 5, 2019Date of Patent: September 6, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ji-Yin Tsai, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen, Yee-Chia Yeo
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Patent number: 11367660Abstract: A device is manufactured by providing a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.Type: GrantFiled: December 14, 2020Date of Patent: June 21, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hsiung Yen, Ta-Chun Ma, Chien-Chang Su, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen
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Publication number: 20210366715Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate, the substrate including silicon, the first fin including silicon germanium; forming an isolation region around the first fin, an oxide layer being formed on the first fin during formation of the isolation region; removing the oxide layer from the first fin with a hydrogen-based etching process, silicon at a surface of the first fin being terminated with hydrogen after the hydrogen-based etching process; desorbing the hydrogen from the silicon at the surface of the first fin to depassivate the silicon; and exchanging the depassivated silicon at the surface of the first fin with germanium at a subsurface of the first fin.Type: ApplicationFiled: August 9, 2021Publication date: November 25, 2021Inventors: Ta-Chun Ma, Yi-Cheng Li, Pin-Ju Liang, Cheng-Po Chau, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen, Cheng-Hsiung Yen
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Patent number: 11087987Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate, the substrate including silicon, the first fin including silicon germanium; forming an isolation region around the first fin, an oxide layer being formed on the first fin during formation of the isolation region; removing the oxide layer from the first fin with a hydrogen-based etching process, silicon at a surface of the first fin being terminated with hydrogen after the hydrogen-based etching process; desorbing the hydrogen from the silicon at the surface of the first fin to depassivate the silicon; and exchanging the depassivated silicon at the surface of the first fin with germanium at a subsurface of the first fin.Type: GrantFiled: July 1, 2019Date of Patent: August 10, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ta-Chun Ma, Yi-Cheng Li, Pin-Ju Liang, Cheng-Po Chau, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen, Cheng-Hsiung Yen
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Publication number: 20210098308Abstract: A device is manufactured by providing a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.Type: ApplicationFiled: December 14, 2020Publication date: April 1, 2021Inventors: Cheng-Hsiung Yen, Ta-Chun Ma, Chien-Chang Su, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen
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Patent number: 10867862Abstract: A device is manufactured by providing a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.Type: GrantFiled: June 17, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hsiung Yen, Ta-Chun Ma, Chien-Chang Su, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen
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Publication number: 20200135467Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate, the substrate including silicon, the first fin including silicon germanium; forming an isolation region around the first fin, an oxide layer being formed on the first fin during formation of the isolation region; removing the oxide layer from the first fin with a hydrogen-based etching process, silicon at a surface of the first fin being terminated with hydrogen after the hydrogen-based etching process; desorbing the hydrogen from the silicon at the surface of the first fin to depassivate the silicon; and exchanging the depassivated silicon at the surface of the first fin with germanium at a subsurface of the first fin.Type: ApplicationFiled: July 1, 2019Publication date: April 30, 2020Inventors: Ta-Chun Ma, Yi-Cheng Li, Pin-Ju Liang, Cheng-Po Chau, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen, Cheng-Hsiung Yen
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Publication number: 20200075729Abstract: A device is manufactured by etching a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.Type: ApplicationFiled: June 17, 2019Publication date: March 5, 2020Inventors: Cheng-Hsiung Yen, Ta-Chun Ma, Chien-Chang Su, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen
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Publication number: 20200006533Abstract: In an embodiment, a device includes: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region including silicon; a second semiconductor region on the first semiconductor region, the second semiconductor region including silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack.Type: ApplicationFiled: April 5, 2019Publication date: January 2, 2020Inventors: Ji-Yin Tsai, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen, Yee-Chia Yeo