Patents by Inventor Jung-Jen Liu

Jung-Jen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8363635
    Abstract: A method and system for reducing power consumption of OFDM (Orthogonal Frequency Division Multiplexing) signal synchronization circuit comprises a sync setting, a sync controller, a sync pipeline and a data corrector. The sync setting dynamically changes correlation data sample rate based on synchronization statuses and results. The sync controller controls and schedules frame and symbol synchronizations, and turns on and off the sync pipeline based on synchronization activities. The sync pipeline integrates frame and symbol synchronization operations, synchronizes receiving signal with scalable synchronization window, synchronization sequence length, synchronization delay and variable data sample rate. Data corrector adjusts input data with coarse timing and fine frequency offsets estimated in sync pipeline, and generates corrected output data for further processing. By using the above techniques, the power consumption of signal synchronization circuit is reduced.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: January 29, 2013
    Inventor: Jung-Jen Liu
  • Publication number: 20100046685
    Abstract: A method and system for reducing power consumption of OFDM (Orthogonal Frequency Division Multiplexing) signal synchronization circuit comprises a sync setting, a sync controller, a sync pipeline and a data corrector. The sync setting dynamically changes correlation data sample rate based on synchronization statuses and results. The sync controller controls and schedules frame and symbol synchronizations, and turns on and off the sync pipeline based on synchronization activities. The sync pipeline integrates frame and symbol synchronization operations, synchronizes receiving signal with scalable synchronization window, synchronization sequence length, synchronization delay and variable data sample rate. Data corrector adjusts input data with coarse timing and fine frequency offsets estimated in sync pipeline, and generates corrected output data for further processing. By using the above techniques, the power consumption of signal synchronization circuit is reduced.
    Type: Application
    Filed: August 20, 2008
    Publication date: February 25, 2010
    Inventor: Jung-Jen Liu
  • Publication number: 20100016768
    Abstract: A vibrating and rolling massage device is wearable on a limb of a user in order to allow the user to carry out massage operation with rolling of the massage device and to provide massage effect simultaneously on the limb wearing the massage device and a part of a human body on which the palm wearing the massage device is positioned. Further, a vibration motor that generates vibration for carrying out massage operation is provided in such a way that the vibration motor is accommodated in a motor holder that can be releasably mounted/dismounted in a tool free manner so that the vibration motor can be selectively set at a position desired by the user.
    Type: Application
    Filed: May 22, 2009
    Publication date: January 21, 2010
    Inventor: Jung-Jen Liu
  • Patent number: 6757760
    Abstract: A dispatching apparatus includes a channel pointer register having storage locations, each with fields for channel number, valid bit, and corresponding instruction pointer which points to instructions for processing data for that channel. When an isochronous channel is allocated for reception, the host programs the channel number and corresponding instruction pointer value into a storage location and sets the corresponding valid bit. When data is received, the channel number is compared to channel numbers within valid storage locations. The data is processed according to instructions located at the corresponding instruction pointer value if there is a channel number match or instructions at the default instruction pointer value if there is no match.
    Type: Grant
    Filed: September 26, 2000
    Date of Patent: June 29, 2004
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventors: Jung-Jen Liu, Bruce A. Fairman
  • Patent number: 6667988
    Abstract: A system and method for multi-level context switching in an electronic network comprises a control state machine configured to implement a data priority scheme, a return address generator configured to hold and release return addresses for interrupted instruction modules in accordance with the data priority scheme and context information from the electronic network, and a processor configured to process data from the electronic network in accordance with the data priority scheme and the context information. Receive registers stores data received from the electronic network. The control state machine includes a switch address generator and a program counter select. The switch address generator outputs a switch address, which is an address for a first instruction for a selected-context instruction module. The return address generator holds and releases the return addresses, which are addresses of next consecutive instructions, when an instruction module is interrupted for a context switch.
    Type: Grant
    Filed: August 14, 2000
    Date of Patent: December 23, 2003
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventors: Jung-Jen Liu, Scott Smyers, Bruce A. Fairman, Steve Pham, Jose L. Diaz, Richard A. Bardini
  • Patent number: 6535940
    Abstract: A system and method for fast data transfers in an electronic network comprises a data transfer engine configured to independently execute data transfer instructions and a processor configured to forward the data transfer instructions to the data transfer engine. The data transfer engine preferably executes the data transfer instructions while the processor proceeds to execute a next instruction. The data transfer engine includes a transmit engine that executes transmit transfer instructions and a receive engine that executes receive transfer instructions. The transmit engine and the receive engine operate independently and thus may operate concurrently.
    Type: Grant
    Filed: July 28, 1999
    Date of Patent: March 18, 2003
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventors: Jung-Jen Liu, Scott Smyers, Bruce A. Fairman, Steve Pham
  • Patent number: 6523108
    Abstract: Deposit and extract instructions include an opcode, a source address, a destination address, a shift number, and a K-bit mask string. The opcode describes the operations to be performed upon a J-bit source string and an N-bit destination string. The source address points to the memory location of the J-bit source string. The destination address points to the memory location of the N-bit destination string. The shift number indicates the number of bits the J-bit source string is to be shifted to generate a shifted bit string. The combination of the shifted bit string with the N-bit destination string is conducted under the control of the K-bit mask string. The invention is useful for high speed digital data processing, such as that performed by devices operating under the IEEE 1394 protocol.
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: February 18, 2003
    Assignees: Sony Corporation, Sony Electronics, Inc.
    Inventors: David James, Jung-Jen Liu
  • Patent number: 6519265
    Abstract: A system and method for context switching in an electronic network comprises a memory configured to store instruction modules, each instruction module corresponding to a context, a processor that executes the instruction modules, and a control state machine. The control state machine selects one of the instruction modules for execution by the processor according to context information from the electronic network. The control state machine includes a switch address generator, a return address register, and a program counter select. The switch address generator outputs a switch address, which is an address for a first instruction for a selected-context instruction module. The return address register stores a return address, which is an address of a next consecutive instruction, when an instruction module is interrupted for a context switch.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: February 11, 2003
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventors: Jung-Jen Liu, Scott Smyers, Bruce A. Fairman, Steve Pham, Jose L. Diaz, Richard A. Bardini
  • Patent number: 6169745
    Abstract: A system and method for multi-level context switching in an electronic network comprises a control state machine configured to implement a data priority scheme, a return address generator configured to hold and release return addresses for interrupted instruction modules in accordance with the data priority scheme and context information from the electronic network, and a processor configured to process data from the electronic network in accordance with the data priority scheme and the context information. Receive registers stores data received from the electronic network. The control state machine includes a switch address generator and a program counter select. The switch address generator outputs a switch address, which is an address for a first instruction for a selected-context instruction module. The return address generator holds and releases the return addresses, which are addresses of next consecutive instructions, when an instruction module is interrupted for a context switch.
    Type: Grant
    Filed: June 18, 1999
    Date of Patent: January 2, 2001
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventors: Jung-Jen Liu, Scott Smyers, Bruce A. Fairman, Steve Pham, Jose L. Diaz, Richard A. Bardini
  • Patent number: 6167471
    Abstract: An apparatus for dispatching a processing element to a program location based on a channel number of received data includes a channel pointer register having a number of storage locations each with a channel number field, a valid bit field and a corresponding instruction pointer field. When an isochronous channel is allocated for use for reception, the host device programs the channel number and a corresponding instruction pointer value into a storage location. When a storage location is programmed, a valid bit within that storage location is also preferably set. The corresponding instruction pointer value points to a series of instructions which are to be used to process data received on that isochronous channel. When isochronous data is then received, the channel number on which the data is received is compared to the channel numbers within the valid storage locations in the channel pointer register.
    Type: Grant
    Filed: October 14, 1998
    Date of Patent: December 26, 2000
    Assignees: Sony Corporation, Sony Electronics, Inc.
    Inventors: Jung-Jen Liu, Bruce A. Fairman
  • Patent number: D604859
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: November 24, 2009
    Inventor: Jung-Jen Liu