Abstract: A word line driving circuit is disclosed which is constituted such that a word line driving circuit is attached to a word line, and an accelerating circuit is added o the word line driving circuit. The word line driving circuit comprises: a NAND gate receiving address signals; an N-MOS transistor 4 with its gate connected to the output terminal of the NAND gate; and an N-MOS transistor 3 with its gate connected through an inverter to the output terminal of the NAND gate; the N-MOS transistor 4 being also connected to a ground terminal Vss and to the N-MOS transistor 3. According to the present invention, the layout area can be kept to the minimum, and the time delay can be prevented during the pull-up and pull-down of the word line.