Patents by Inventor Jung-Keun Lee

Jung-Keun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9288041
    Abstract: An apparatus and method for performing a compression operation in a fast message hash algorithm, which receive a 512-bit message and 512-bit chaining variable data, repeatedly calculate a 128-bit register-based step function, and then produce updated 512-bit chaining variable data. For this, the apparatus for performing a compression operation in a hash algorithm includes a message extension unit for receiving a message and generating a plurality of extended messages. A chaining variable initial conversion unit receives chaining variable data and converts the chaining variable data into initial state data. A step function operation unit repeatedly calculates a step function based on the initial state data and the plurality of extended messages and produces final state data. A chaining variable final conversion unit generates updated chaining variable data from the chaining variable data using the final state data, and outputs the updated chaining variable data.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: March 15, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Deukjo Hong, Dong-Chan Kim, Jung Keun Lee, Daesung Kwon
  • Publication number: 20160056954
    Abstract: An apparatus and method for providing a Feistel-based variable length block cipher, which are configured to when plaintext having a certain bit length is encrypted, generate ciphertext having the same bit length as plaintext, and to decrypt ciphertext into plaintext having the same bit length. The apparatus includes an encryption/decryption key generation unit for generating a number of encryption/decryption keys corresponding to a preset number of rounds, based on a secret key, the length of the secret key, the length of plaintext, and a round constant; an encryption/decryption tweak generation unit for generating an encryption/decryption tweak based on a tweak, a length of tweak, and the length of plaintext; and a ciphertext output unit for outputting ciphertext having length identical to that of plaintext, based on plaintext, the length of the plaintext, the length of the secret key, the encryption/decryption keys, and the encryption/decryption tweak.
    Type: Application
    Filed: July 28, 2015
    Publication date: February 25, 2016
    Inventors: Jung Keun LEE, Bonwook KOO, Dongyoung ROH, Woo-Hwan KIM, Daesung KWON
  • Patent number: 9049007
    Abstract: An encryption apparatus and method that provide a mobile fast block cipher algorithm that supports low-power encryption. The encryption apparatus includes a user interface unit, a key scheduler unit, an initial conversion unit, a round function processing unit, and a final conversion unit. The user interface unit receives plain text to be encrypted and a master key. The key scheduler unit generates a round key from the master key. The initial conversion unit generates initial round function values from the plain text. The round function processing unit repeatedly processes a round function using the round key and the initial round function values. The final conversion unit generates ciphertext from the resulting values of the round function processed in a final round by the round function processing unit.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: June 2, 2015
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Deukjo Hong, Jung Keun Lee, Dong-Chan Kim, Daesung Kwon, Kwon Ho Ryu
  • Publication number: 20150032704
    Abstract: An apparatus and method for performing a compression operation in a hash algorithm are provided. The apparatus includes an interface unit, a message extension unit, a chain variable initial conversion unit, a compression function computation unit, and a chain variable final conversion unit. The interface unit receives a message and chain variable data. The message extension unit generates a plurality of extended messages from the message. The chain variable initial conversion unit converts the chain variable data into initial state data for a compression function. The compression function computation unit repeatedly computes extended message binding and step functions based on the initial state data and the plurality of extended messages, and performs combination with a final extended message, thereby computing final state data. The chain variable final conversion unit generates and outputs chain variable data, into which the chain variable data has been updated, using the final state data.
    Type: Application
    Filed: June 16, 2014
    Publication date: January 29, 2015
    Inventors: Dong-Chan KIM, Deukjo HONG, Jung Keun LEE, Daesung KWON
  • Publication number: 20150005980
    Abstract: A method of controlling a temperature of a terminal apparatus includes measuring a first temperature of a heat source area where at least one heat source is included in the terminal apparatus, and measuring a second temperature of an external area that is distant from the heat source area; determining a difference between the first temperature and the second temperature; and controlling heat generated from the heat source, based on the difference between the first temperature and the second temperature.
    Type: Application
    Filed: June 5, 2014
    Publication date: January 1, 2015
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Min-Soo KIM, Jung-Keun LEE, Ji-Woong OH
  • Publication number: 20140355755
    Abstract: An apparatus and method for performing a compression operation in a fast message hash algorithm, which receive a 512-bit message and 512-bit chaining variable data, repeatedly calculate a 128-bit register-based step function, and then produce updated 512-bit chaining variable data. For this, the apparatus for performing a compression operation in a hash algorithm includes a message extension unit for receiving a message and generating a plurality of extended messages. A chaining variable initial conversion unit receives chaining variable data and converts the chaining variable data into initial state data. A step function operation unit repeatedly calculates a step function based on the initial state data and the plurality of extended messages and produces final state data. A chaining variable final conversion unit generates updated chaining variable data from the chaining variable data using the final state data, and outputs the updated chaining variable data.
    Type: Application
    Filed: January 15, 2014
    Publication date: December 4, 2014
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Deukjo HONG, Dong-Chan KIM, Jung Keun LEE, Daesung KWON
  • Publication number: 20130336480
    Abstract: An encryption apparatus and method that provide a mobile fast block cipher algorithm that supports low-power encryption. The encryption apparatus includes a user interface unit, a key scheduler unit, an initial conversion unit, a round function processing unit, and a final conversion unit. The user interface unit receives plain text to be encrypted and a master key. The key scheduler unit generates a round key from the master key. The initial conversion unit generates initial round function values from the plain text. The round function processing unit repeatedly processes a round function using the round key and the initial round function values. The final conversion unit generates ciphertext from the resulting values of the round function processed in a final round by the round function processing unit.
    Type: Application
    Filed: June 4, 2013
    Publication date: December 19, 2013
    Inventors: Deukjo HONG, Jung Keun LEE, Dong-Chan KIM, Daesung KWON, Kwon Ho RYU
  • Patent number: 8151087
    Abstract: Provided are a cache memory using a linear hash function and a method of operating the same. The cache memory includes: a first hash function module for converting a main memory address received from a central processing unit (CPU) into a first index value using a first hash function; a second hash function module for converting the main memory address into a second index value using a second hash function; a first comparator for comparing a tag value of a data block located at the first index value in the first bank with a tag value of the main memory address; and a second comparator for comparing a tag value of a data block located at the second index value in the second bank with the tag value of the main memory address.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: April 3, 2012
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jung Keun Lee, Sang Woo Park
  • Patent number: 8090098
    Abstract: Provided are a method of generating a Message Authentication Code (MAC) using a stream cipher, and authentication/encryption and authentication/decryption methods using a stream cipher. According to the methods, authentication/encryption is performed using a MAC generated using a stream cipher as an initialization vector of the stream cipher. Therefore, it is unnecessary to use a random number generation algorithm to generate the initialization vector, and thus implementation efficiency can be improved. In addition, upon generation of a MAC, a plurality of key stream generators perform computation for a plurality of message blocks, respectively. Therefore, the message blocks are computed in parallel at a time, and thus computation efficiency is excellent.
    Type: Grant
    Filed: November 12, 2007
    Date of Patent: January 3, 2012
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Woo Hwan Kim, Jung Keun Lee
  • Publication number: 20090132784
    Abstract: Provided are a cache memory using a linear hash function and a method of operating the same. The cache memory includes: a first hash function module for converting a main memory address received from a central processing unit (CPU) into a first index value using a first hash function; a second hash function module for converting the main memory address into a second index value using a second hash function; a first comparator for comparing a tag value of a data block located at the first index value in the first bank with a tag value of the main memory address; and a second comparator for comparing a tag value of a data block located at the second index value in the second bank with the tag value of the main memory address.
    Type: Application
    Filed: March 28, 2008
    Publication date: May 21, 2009
    Inventors: Jung Keun Lee, Sang Woo Park
  • Publication number: 20080112561
    Abstract: Provided are a method of generating a Message Authentication Code (MAC) using a stream cipher, and authentication/encryption and authentication/decryption methods using a stream cipher. According to the methods, authentication/encryption is performed using a MAC generated using a stream cipher as an initialization vector of the stream cipher. Therefore, it is unnecessary to use a random number generation algorithm to generate the initialization vector, and thus implementation efficiency can be improved. In addition, upon generation of a MAC, a plurality of key stream generators perform computation for a plurality of message blocks, respectively. Therefore, the message blocks are computed in parallel at a time, and thus computation efficiency is excellent.
    Type: Application
    Filed: November 12, 2007
    Publication date: May 15, 2008
    Inventors: Woo Hwan KIM, Jung Keun LEE
  • Patent number: 6530001
    Abstract: A computer system controlling a memory clock signal of a DIMM (dual in-line memory module) socket is described and which includes a processor controlling a 66 MHz or a 100 MHz system bus clock signal to be generated, a DIMM memory module supporting the 66 MHz or the 100 MH system bus clock signal, a clock generator generating the 66 MHz or the 100 MHz system bus clock signal by receiving control of the processor, a clock buffer, a first and a second system controllers. The clock generator and the clock buffer store setting data according to memory data of a memory module from a first system controller. The first and the second system controllers control a memory bus clock signal corresponding to an inserted single-sided type or double-sided type DIMM memory module to be outputted.
    Type: Grant
    Filed: October 18, 1999
    Date of Patent: March 4, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jung-Keun Lee
  • Patent number: 6010637
    Abstract: A method for preparing a sample for its optical analysis in the manufacture of a semiconductor device includes the step of drying a liquid formed on the semiconductor wafer until the concentration of contaminants contained in the liquid is of a sufficiently high level for the optical analyzer to adequately detect the contaminants. The liquid may be of a film formed on the wafer and dissolved into liquid drops, or deionized water or various chemicals to which the wafer is exposed during a manufacturing process. The apparatus includes a chuck for bringing the wafer into and out of a processing chamber, a guide for guiding the chuck, a piston cylinder for driving the chuck along the guide to a processing position, and a gas supplying system which directs nitrogen gas onto the wafer for drying the liquid. Appropriate controls are provided so that the apparatus can be operated automatically or manually.
    Type: Grant
    Filed: March 4, 1998
    Date of Patent: January 4, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chun-deuk Lee, Kyoung-seop Lee, Hyun-woon Lee, Jung-keun Lee