Abstract: Some embodiments relate to an integrated circuit (IC) device that includes a first substrate including an optical lens at a frontside surface of the first substrate, an electrical IC structure disposed proximate a backside surface of the first substrate, and a photonic IC structure disposed proximate a backside surface of the electrical IC structure. The photonic IC structure includes a second substrate providing a backside surface of the photonic IC structure; a photodetector, a grating coupler, and an inverse grating coupler disposed over a frontside surface of the second substrate; and a reflector disposed at a frontside surface of the photonic IC structure. The grating coupler and the inverse grating coupler are configured to direct light from the optical lens and the backside surface of the second substrate, respectively, to the photodetector. The reflector is configured to direct light from the inverse grating coupler back to the inverse grating coupler.

Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a source/drain region disposed over a substrate, a gate electrode layer disposed over the substrate, a first gate spacer disposed between the gate electrode layer and the source/drain region, and a dielectric spacer disposed between the gate electrode layer and the source/drain region. A first portion of the dielectric spacer is in contact with a first portion of the first gate spacer. The structure further includes a sacrificial layer disposed between a second portion of the first gate spacer and a second portion of the dielectric spacer.

Abstract: Various embodiments include protection layers for a transistor and methods of forming the same. In an embodiment, a method includes: exposing a semiconductor nanostructure, a dummy nanostructure, and an isolation region by removing a dummy gate; increasing a deposition selectivity between a top surface of the semiconductor nanostructure and a top surface of the isolation region relative a selective deposition process; depositing a protection layer on the top surface of the isolation region by performing the selective deposition process; removing the dummy nanostructure by selectively etching a dummy material of the dummy nanostructure at a faster rate than a protection material of the protection layer; and forming a gate structure around the semiconductor nanostructure.

Abstract: The present disclosure provides a method for fabricating a semiconductor structure, including bonding a capping substrate over a sensing substrate, forming a through hole traversing the capping substrate, forming a dielectric layer over the capping substrate under a first vacuum level, and forming a metal layer over the dielectric layer under a second vacuum level, wherein the second vacuum level is higher than the first vacuum level.

Abstract: An optical fingerprint sensor configured to be arranged under an at least partially transparent display panel comprises an array of color controllable light sources. The optical fingerprint sensor comprises an image sensor comprising a photodetector pixel array; an array of microlenses arranged under the color controllable light sources; a color filter layer arranged under the array of microlenses comprising alternating filter element types of different colors for adjacent subsets of pixels in the photodetector pixel array. The color controllable light sources are controllable, in response to a first finger condition, to emit light of uniform color being a mix of the colors of the filter elements, and in response to a second finger condition, to emit a color pattern including the colors of the filter elements, wherein groups of color controllable light sources are controlled to emit light corresponding to a color of the filter elements.

Abstract: Semiconductor structures and methods of forming the same are provided. An exemplary method includes depositing a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer over a bottom epitaxial source/drain feature formed in a bottom portion of a source/drain trench, etching back the CESL and the ILD layer to expose a top portion of the source/drain trench, performing a plasma-enhanced atomic layer deposition process (PEALD) to form an insulating layer over the source/drain trench, where the insulating layer comprises a non-uniform deposition thickness and comprises a first portion in direct contact with the ILD layer and a second portion extending along a sidewall surface of the top portion of the source/drain trench. Method also includes removing the second portion of the insulating layer and forming a top bottom epitaxial source/drain feature on the second portion of the insulating layer and in the source/drain trench.

Abstract: A photonic package includes an optical die and an electronic die. The optical die has a first side and a second side opposite to the first side. The optical die includes a first grating coupler, a second grating coupler separated from the first grating coupler and an interconnect structure disposed over the first side. The first grating coupler includes a plurality of first segments disposed over the first side, and the second grating coupler includes a plurality of second segments disposed over the first side. The first segments and the second segments include a same material. The interconnect structure is disposed between the electronic die and the optical die. The optical die and the electronic die are electrically connected to each other through the interconnect structure. The first segments are in contact with the interconnect structure, and the second segments are separated from the interconnect structure.

Abstract: A power plug with thermal insulation-function has an output connector having a wire connecting end, an internal module, a housing, and an external module. The internal module has an outer surface and encloses the wire connecting end of the output connector. A plurality of recesses are concavely formed on the outer surface of the internal module. The housing encloses the outer surface of the internal module, wherein a plurality of gas cells are formed between the housing and each of the plurality of recesses. The external module encloses the housing and the internal module. Air can be stored in the gas cells for insulating thermal conduction from inside to outside. Heat can hardly transfer from the internal module to the external module to dissipate via the outer surface of the external module, thereby lowering the surface temperature of the external module to avoid burning the user.

Abstract: A heat dissipating structure of a power supply is disposed on an inner side of a casing and has two heat dissipating covers configured to be connected with each other, and a heat dissipating sleeve annularly mounted on and around the two heat dissipating covers and disposed between the heat dissipating covers and the casing. The heat dissipating sleeve is able to be bent according to an internal structure of the casing for attaching to the casing and increasing contact area between the heat dissipating sleeve and the casing. The heat from an interior of the power supply can be conducted to the two heat dissipating covers for a first heat spreading and then to the heat dissipating sleeve for a second heat spreading. Thus, speed of heat dissipation to an exterior of the casing can be increased and temperature inside the power supply can be effectively reduced.

Abstract: A semiconductor device in a first area includes first non-planar semiconductor structures separated with a first distance, and a first isolation region including a first layer and a second layer that collectively embed a lower portion of each of the first non-planar semiconductor structures. At least one of the first layer or second layer of the first isolation region is in a cured state. The semiconductor device in a second area includes second non-planar semiconductor structures separated with a second distance, and a second isolation region including a first layer and a second layer that collectively embed a lower portion of each of the second non-planar semiconductor structures. At least one of the first or second layer of the second isolation region is in a cured state.

Abstract: A method for forming a semiconductor structure includes following operations. An interconnect structure is formed over a substrate. The interconnect structure includes a top conductive layer. A dielectric structure is formed over the interconnect structure. The dielectric structure is patterned to simultaneously form a cavity and a protrusion in the cavity. A MEMS substrate is bonded to the dielectric structure to seal the cavity. The protrusion is separated from the MEMS substrate.

Abstract: A method for forming a semiconductor device includes receiving a first bonded to a second substrate by a dielectric layer, wherein a conductive layer is disposed in the dielectric layer and a cavity is formed between the first substrate, the second substrate and the dielectric layer; forming a via opening in the second substrate to expose the conductive layer and a vent hole in the substrate to couple to the cavity; forming a first buffer layer covering sidewalls of the via opening and a second buffer layer covering sidewalls of the vent hole; and forming a connecting structure in the via opening and a sealing structure to seal the vent hole.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a gate electrode disposed over a semiconductor substrate and a gate cut-fill structure disposed in the gate electrode to separate the gate electrode into two portions. The gate cut-fill structure includes a first liner, a second liner disposed on the first liner, and a dielectric material disposed on the second liner. The dielectric material has a “V” shaped cross-section.

Abstract: Aspects of the subject technology provide improved point-to-point audio communications based on human variable sensitivity to latency differences in multipath communications. In aspects, improved techniques may include measuring a level of ambient noise, and then selecting processing for a received electronic audio based on the measured level of ambient noise before emitting the processed audio signal at a loudspeaker worn by a listener.

Abstract: A semiconductor device in a first area includes first non-planar semiconductor structures separated with a first distance, and a first isolation region including a first layer and a second layer that collectively embed a lower portion of each of the first non-planar semiconductor structures. At least one of the first layer or second layer of the first isolation region is in a cured state. The semiconductor device in a second area includes second non-planar semiconductor structures separated with a second distance, and a second isolation region including a first layer and a second layer that collectively embed a lower portion of each of the second non-planar semiconductor structures. At least one of the first or second layer of the second isolation region is in a cured state.

Abstract: A semiconductor structure includes a substrate, a MEMS substrate, a dielectric structure between the substrate and the MEMS substrate, a cavity in the dielectric structure, an electrode over the substrate, and a protrusion disposed in the cavity. The MEMS substrate includes a movable membrane, and the cavity is sealed by the movable membrane. A height of the protrusion is less than a depth of the cavity.

Abstract: A display control method applicable to an all-in-one (AIO) computer is provided. The AIO computer includes a first monitor and a second monitor. The display control method includes: receiving a control instruction from the first monitor; projecting a display content on the second monitor according to the control instruction; and selectively enabling a touch control function of the second monitor according to the control instruction.

Abstract: A device includes first and second gate structures respectively extending across the first and second fins, and a gate isolation plug between a longitudinal end of the first gate structure and a longitudinal end of the second gate structure. The gate isolation plug comprises a first dielectric layer and a second dielectric layer over the first dielectric layer. The first dielectric layer has an upper portion and a lower portion below the upper portion. The upper portion has a thickness smaller than a thickness of the lower portion of the first dielectric layer.

Abstract: Aspects of the subject technology provide improved point-to-point audio communications based on human variable sensitivity to latency differences in multipath communications. In aspects, improved techniques may include measuring a level of ambient noise, and then selecting processing for a received electronic audio based on the measured level of ambient noise before emitting the processed audio signal at a loudspeaker worn by a listener.

Abstract: A method includes etching a gate stack in a wafer to form a trench, depositing a silicon nitride liner extending into the trench, and depositing a silicon oxide layer. The process of depositing the silicon oxide layer includes performing a treatment process on the wafer using a process gas including nitrogen and hydrogen, and performing a soaking process on the wafer using a silicon precursor.