Abstract: A thin film transistor array panel includes: a gate wiring layer disposed on a substrate; an oxide semiconductor layer disposed on the gate wiring layer; and a data wiring layer disposed on the oxide semiconductor layer, in which the data wiring layer includes a main wiring layer including copper and a capping layer disposed on the main wiring layer and including a copper alloy.

Abstract: A thin film transistor (TFT) includes a semiconductor active layer, a gate electrode, a source electrode, and a drain electrode. The semiconductor active layer includes a first doped region as a source region, a second doped region as a drain region, an undoped region between the first and second doped regions. A third doped region is disposed between the second doped region and the undoped region. The gate electrode is insulated from the semiconductor active layer and overlaps the third doped region and the undoped region. The source electrode and the drain electrode are connected to the first and second doped regions.

Abstract: A polarizing plate includes a polarizer having absorption and transmission axes, a protective film on an upper surface of the polarizer, a half-wavelength (?/2) retardation film on a lower surface of the polarizer, an adhesive layer on a lower surface of the half-wavelength (?/2) retardation film, and a quarter-wavelength (?/4) retardation film on a lower surface of the adhesive layer. An absolute orthogonal b-coordinate value based on a CIELAB color coordinate system of the polarizing plate may be approximately 3 or less when the polarizing plate is stacked with a reference polarizing plate having a degree of polarization of at least 99.9% such that an angle between the absorption axis of the polarizer and an absorption axis of a polarizer of the reference polarizing plate or an angle between the transmission axis of the polarizer and a transmission axis of the polarizer of the reference polarizing plate is 90°.

Abstract: Provided is a thin film transistor array panel. The thin film transistor array panel according to exemplary embodiments of the present invention includes: a gate wiring layer disposed on a substrate; an oxide semiconductor layer disposed on the gate wiring layer; and a data wiring layer disposed on the oxide semiconductor layer, in which the data wiring layer includes a main wiring layer including copper and a capping layer disposed on the main wiring layer and including a copper alloy.

Abstract: A thin film transistor substrate includes a semiconductor pattern on a base substrate, a first insulation member disposed on the semiconductor pattern, a second insulation pattern disposed on the first insulation member, and a gate electrode disposed on the first insulation member and the second insulation pattern. The second insulation pattern overlaps a first end portion of the semiconductor pattern, and exposes a second end portion of the semiconductor pattern opposite to the first end portion. The gate electrode overlaps both the first insulation member and the second insulation pattern.

Abstract: A method of manufacturing a thin film transistor (TFT) array substrate is disclosed. In one aspect, the method includes forming an active layer on a substrate, forming a first insulating layer on the substrate to cover the active layer, and forming a first gate electrode on the first insulating layer in an area corresponding to the active layer, doping the active layer with ion impurities, forming a second insulating layer on the first insulating layer to cover the first gate electrode, performing an annealing process on the active layer, forming a lower electrode of a capacitor on the second insulating layer, forming a third insulating layer on the second insulating layer to cover the lower electrode, wherein the third insulating layer has a dielectric constant that is greater than those of the first and second insulating layers, and forming an upper electrode of the capacitor on the third insulating layer.

Abstract: A display device includes a substrate, an active layer, a gate insulation layer, a gate electrode, an interlayer insulation layer, a clad layer, a source electrode, and a drain electrode. The active layer is disposed on the substrate. The gate insulation layer is disposed on the active layer. The gate electrode is disposed on the gate insulation layer. The interlayer insulation layer is disposed on the gate electrode. A dielectric constant of the interlayer insulation layer is less than a dielectric constant of the gate insulation layer. The clad layer is disposed on the interlayer insulation layer. The source and drain electrodes are disposed on the clad layer.

Abstract: A thin film transistor substrate includes a semiconductor pattern on a base substrate, a first insulation member disposed on the semiconductor pattern, a second insulation pattern disposed on the first insulation member, and a gate electrode disposed on the first insulation member and the second insulation pattern. The second insulation pattern overlaps a first end portion of the semiconductor pattern, and exposes a second end portion of the semiconductor pattern opposite to the first end portion. The gate electrode overlaps both the first insulation member and the second insulation pattern.

Abstract: A thin film transistor (TFT) includes a semiconductor active layer, a gate electrode, a source electrode, and a drain electrode. The semiconductor active layer includes a first doped region as a source region, a second doped region as a drain region, an undoped region between the first and second doped regions. A third doped region is disposed between the second doped region and the undoped region. The gate electrode is insulated from the semiconductor active layer and overlaps the third doped region and the undoped region. The source electrode and the drain electrode are connected to the first and second doped regions.

Abstract: A display substrate includes a base substrate, a switching element, a gate line, a data line and a pixel electrode. Each of the gate line and the data line includes a first metal layer, and a second metal layer directly on the first metal layer. The switching element is on the base substrate, and includes a control electrode and an input electrode or an output electrode. The control electrode includes the first metal layer and excludes the second metal layer, and extends from the gate line. The input electrode or the output electrode includes a second metal layer and excludes the first metal layer. The input electrode extends from the data line. The pixel electrode is electrically connected to the output electrode of the switching element through a first contact hole, and includes a transparent conductive layer.

Abstract: A method of manufacturing a thin film transistor (TFT) array substrate is disclosed. In one aspect, the method includes forming an active layer on a substrate, forming a first insulating layer on the substrate to cover the active layer, and forming a first gate electrode on the first insulating layer in an area corresponding to the active layer, doping the active layer with ion impurities, forming a second insulating layer on the first insulating layer to cover the first gate electrode, performing an annealing process on the active layer, forming a lower electrode of a capacitor on the second insulating layer, forming a third insulating layer on the second insulating layer to cover the lower electrode, wherein the third insulating layer has a dielectric constant that is greater than those of the first and second insulating layers, and forming an upper electrode of the capacitor on the third insulating layer.

Abstract: A thin film transistor substrate includes a semiconductor pattern on a base substrate, a first insulation member disposed on the semiconductor pattern, a second insulation pattern disposed on the first insulation member, and a gate electrode disposed on the first insulation member and the second insulation pattern. The second insulation pattern overlaps a first end portion of the semiconductor pattern, and exposes a second end portion of the semiconductor pattern opposite to the first end portion. The gate electrode overlaps both the first insulation member and the second insulation pattern.

Abstract: A display device includes a substrate, an active layer, a gate insulation layer, a gate electrode, an interlayer insulation layer, a clad layer, a source electrode, and a drain electrode. The active layer is disposed on the substrate. The gate insulation layer is disposed on the active layer. The gate electrode is disposed on the gate insulation layer. The interlayer insulation layer is disposed on the gate electrode. A dielectric constant of the interlayer insulation layer is less than a dielectric constant of the gate insulation layer. The clad layer is disposed on the interlayer insulation layer. The source and drain electrodes are disposed on the clad layer.

Abstract: A thin film transistor array panel may include a channel layer including an oxide semiconductor and formed in a semiconductor layer, a source electrode formed in the semiconductor layer and connected to the channel layer at a first side, a drain electrode formed in the semiconductor layer and connected to the channel layer at an opposing second side, a pixel electrode formed in the semiconductor layer in a same portion of the semiconductor layer as the drain electrode, an insulating layer disposed on the channel layer, a gate line including a gate electrode disposed on the insulating layer, a passivation layer disposed on the source and drain electrodes, the pixel electrode, and the gate line, and a data line disposed on the passivation layer. A width of the channel layer may be substantially equal to a width of the pixel electrode in a direction parallel to the gate line.

Abstract: A polarizing plate includes a polarizer, a protective film on an upper surface of the polarizer, a half-wavelength (?/2) retardation film on a lower surface of the polarizer, an adhesive layer on a lower surface of the half-wavelength (?/2) retardation film, and a quarter-wavelength (?/4) retardation film on a lower surface of the adhesive layer. The half-wavelength (?/2) retardation film may have a refractive index n1, the quarter-wavelength (?/4) retardation film may have a refractive index n2, and the adhesive layer may have a refractive index n in the range of n1<n<n2 or n2<n<n1. An optical display apparatus may include the polarizing plate, and further a window on a top surface of the polarizing plate, a conductor on a bottom surface of the polarizing plate, an optical display device on a bottom surface of the conductor, and a substrate on a bottom surface of the optical display device.

Abstract: A polarizing plate includes a polarizer having absorption and transmission axes, a protective film on an upper surface of the polarizer, a half-wavelength (?/2) retardation film on a lower surface of the polarizer, an adhesive layer on a lower surface of the half-wavelength (?/2) retardation film, and a quarter-wavelength (?/4) retardation film on a lower surface of the adhesive layer. An absolute orthogonal b-coordinate value based on a CIELAB color coordinate system of the polarizing plate may be approximately 3 or less when the polarizing plate is stacked with a reference polarizing plate having a degree of polarization of at least 99.9% such that an angle between the absorption axis of the polarizer and an absorption axis of a polarizer of the reference polarizing plate or an angle between the transmission axis of the polarizer and a transmission axis of the polarizer of the reference polarizing plate is 90°.

Abstract: A carbon substrate for a gas diffusion layer that has a porosity gradient in a thickness direction thereof, a gas diffusion using the carbon substrate, an electrode and a membrane-electrode assembly for a fuel cell that include the gas diffusion layer, and a fuel cell including the membrane-electrode assembly having the gas diffusion layer are provided. The gas diffusion layer has improved water discharge ability and improved bending strength both in the machine direction and cross-machine direction.

Abstract: A wireless localization technology using efficient multilateration in a wireless sensor network is disclosed. After calculating estimated distances from each of at least three reference nodes to a blind node using received signal strength of wireless signals that the at least three reference nodes received from the blind node, the estimated location of the blind node is obtained through multilateration using the calculated estimated distances. To correct error in the estimated location, the estimated distances are used, and the error correction direction and error correction distance for the estimated location are calculated by applying a largest weight to the reference node closest to the estimated location. The error of the estimated location is corrected by move the estimated location of the blind node by the calculated error correction direction and error correction distance. Calculation for the error correction is very simple and fast.

Abstract: A display substrate includes a base substrate, a switching element, a gate line, a data line and a pixel electrode. Each of the gate line and the data line includes a first metal layer, and a second metal layer directly on the first metal layer. The switching element is on the base substrate, and includes a control electrode and an input electrode or an output electrode. The control electrode includes the first metal layer and excludes the second metal layer, and extends from the gate line. The input electrode or the output electrode includes a second metal layer and excludes the first metal layer. The input electrode extends from the data line. The pixel electrode is electrically connected to the output electrode of the switching element through a first contact hole, and includes a transparent conductive layer.

Abstract: A wireless localization technology using efficient multilateration in a wireless sensor network is disclosed. After calculating estimated distances from each of at least three reference nodes to a blind node using received signal strength of wireless signals that the at least three reference nodes received from the blind node, the estimated location of the blind node is obtained through multilateration using the calculated estimated distances. To correct error in the estimated location, the estimated distances are used, and the error correction direction and error correction distance for the estimated location are calculated by applying a largest weight to the reference node closest to the estimated location. The error of the estimated location is corrected by move the estimated location of the blind node by the calculated error correction direction and error correction distance. Calculation for the error correction is very simple and fast.