Patents by Inventor Jung-Liang CHIEN

Jung-Liang CHIEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for die to die stress improvement
    Patent number: 9171759
    Abstract: A semiconductor wafer having a plurality of chip die areas arranged on a wafer in an array, each chip die area including a seal ring area with one or more first sets of polygonal structures. The wafer further comprises scribe line areas between the chip die areas, the scribe line areas including one or more second sets of polygonal structures. The presence of proximate polygonal structures between the scribe line and seal ring areas balance stresses between the chip die areas during wafer dicing operation.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: October 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Pin Cheng, Jung-Liang Chien, Chih-Kang Chao, Chi-Cherng Jeng, Hsin-Chi Chen, Ying-Lang Wang
  • Black Level Control for Image Sensors
    Publication number: 20140211057
    Abstract: An embodiment image sensor includes a pixel region spaced apart from a black level control (BLC) region by a buffer region. In an embodiment, a light shield is disposed over the BLC region and extends into the buffer region. In an embodiment, the buffer region includes an array of dummy pixels. Such embodiments effectively reduce light cross talk at the edge of the BLC region, which permits more accurate black level calibration. Thus, the image sensor is capable of producing higher quality images.
    Type: Application
    Filed: July 17, 2013
    Publication date: July 31, 2014
    Inventors: Jung-Liang Chien, Yun-Wei Cheng, Che-Min Lin, Shiu-Ko JangJian, Chi-Cherng Jeng, Chih-Mu Huang
  • SYSTEM AND METHOD FOR DIE TO DIE STRESS IMPROVEMENT
    Publication number: 20140167199
    Abstract: A semiconductor wafer having a plurality of chip die areas arranged on a wafer in an array, each chip die area including a seal ring area with one or more first sets of polygonal structures. The wafer further comprises scribe line areas between the chip die areas, the scribe line areas including one or more second sets of polygonal structures. The presence of proximate polygonal structures between the scribe line and seal ring areas balance stresses between the chip die areas during wafer dicing operation.
    Type: Application
    Filed: December 18, 2012
    Publication date: June 19, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Pin CHENG, Jung-Liang CHIEN, Chih-Kang CHAO, Chi-Cherng JENG, Hsin-Chi CHEN, Ying-Lang WANG