Abstract: Methods, systems, processing units, and signals for transferring data of various data types across a common data path interface are disclosed. A representative method for transferring data between a master processing unit and at least a first slave processing unit via a common data path interface, the master processing unit and the at least first slave processing unit are configured to process a plurality of non-Asynchronous Transfer Mode (ATM) data types, includes: receiving the data; generating an ATM cell in an ATM cell format determined from a plurality of ATM cell formats; transferring the ATM cell across the common data path interface to an appropriate processing unit; and processing the ATM cell upon receiving it from the common data path interface.

Abstract: Methods, systems, processing units, and signals for transferring data of various data types across a common data path interface are disclosed. A representative method for transferring data between a master processing unit and at least a first slave processing unit via a common data path interface, the master processing unit and the at least first slave processing unit are configured to process a plurality of non-Asynchronous Transfer Mode (ATM) data types, includes: receiving the data; generating an ATM cell in an ATM cell format determined from a plurality of ATM cell formats; transferring the ATM cell across the common data path interface to an appropriate processing unit; and processing the ATM cell upon receiving it from the common data path interface.

Abstract: Methods, systems, processing units, and signals for transferring data of various data types across a common data path interface are disclosed. A representative method for transferring data between a master processing unit and at least a first slave processing unit via a common data path interface, the master processing unit and the at least first slave processing unit are configured to process a plurality of non-Asynchronous Transfer Mode (ATM) data types, includes: receiving the data; generating an ATM cell in an ATM cell format determined from a plurality of ATM cell formats; transferring the ATM cell across the common data path interface to an appropriate processing unit; and processing the ATM cell upon receiving it from the common data path interface.

Abstract: A system and method for reducing transmit carrier wander in a DSL communication system are disclosed. A network timing reference unit provides an automatic embedded solution for synchronizing DSL frames to an external communication system reference clock. The network timing reference unit applies or removes bits to adjust the length of a DSL frame in response to a sliding window state table. A sliding window is selected in response to the relative position of the DSL frame to a system clock reference point over a number of DSL frames. A network timing reference unit in accordance with the present invention may comprise a counter, a network timing latch, a synchronization word detector, a DSL frame latch, a lead/lag comparator, a sliding window buffer, a sliding window state table, a DSL frame state recorder, and a sensitivity buffer. The present invention provides a method for reducing transmit carrier wander in a DSL transceiver.

Abstract: The invention provides a DRR protocol that uses the Z-bit signaling channel that is robust, enables activating and deactivating bit synchronous PCM voice timeslots in a very short period of time, supports the ability to handle multiple simultaneous voice call establishments and clearings and supports periodically refreshing the status of the bit synchronous PCM timeslots.

Abstract: This contribution provides a framework for defining the transport of channelized voice applications over SDSL. The framework includes a reference model, and identifies some operations and functions for supporting channelized voice.

Abstract: The invention provides a system and method for enabling DRR that supports multiple, simultaneous voice call events. In addition the invention provides for DRR that support the activation and deactivation of bit synchronous PCM timeslots within a well-defined period of time (e.g. not to exceed 100 ms) that can accommodate any voice call control signaling procedures, DRR that provides for robust communication of the DRR signaling protocol between the line terminal (LT) and the network terminal (NT), DRR that supports periodically refreshing the status of the bit synchronous PCM timeslots and DRR that aligns with proposed DSL bearer requirements.

Abstract: In general, the multi-mode analog front-end provides an internal line driver and hybrid, as well as numerous functions, in order to provide a close to optimum solution for all digital subscriber line applications. The functions provided for by the analog front-end include; programmable hybrid attenuation; onboard amplifiers for driving external transmit and receive filters; a line driver with programmable drive and gain; programmable RC-filters capable of calibration via an internal loop-back under digital control; a programmable switched-capacitor filter for tracking the over sampling rate used by a digital signal processor; internal testing functions; a high frequency boost circuit; a dual input peak detector; selectable data rates; and a programmable data interface. The analog front-end allows for use of particular blocks within the analog front-end particular to the functions necessary to compensate for a particular digital subscriber line application.

Abstract: A phase difference measuring device includes a phase detector, a low-pass filter/voltage controlled oscillator, a reference signal selector for selecting either an internal reference signal or an external reference signal as a reference signal, a phase comparator for comparing an undertest signal with the selected reference signal and obtaining a phase difference between the two compared signal. The internal reference signal is selected when the undertest signal is a jittering signal, and the external reference signal is selected when the undertest signal is a wandering signal. The undertest signal, the selected reference signal, and a relatively high frequency clock signal from external are sent to the phase comparator and a phase difference between the undertest signal and the selected reference signal is counted by the relatively high frequency clock signal.