Patents by Inventor Jung-Mi KO

Jung-Mi KO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10998053
    Abstract: A memory device includes: a memory block, coupled to a plurality of word lines; a peripheral circuit for performing a sensing operation on selected memory cells of the memory block, the select memory cells being coupled to a selected word line of the plurality of word lines; a word line voltage controller for controlling a sensing voltage applied to the selected word line to perform the sensing operation on the selected memory cells and configured to control a pass voltage applied to the selected word line and unselected word lines of the plurality of word lines, coupled to the memory block; and a bit line control signal generator for controlling the peripheral circuit to apply a channel precharge voltage to respective bit lines, coupled to the selected memory cells, while the pass voltage is being applied to the selected word line and the unselected word lines.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: May 4, 2021
    Assignee: SK hynix Inc.
    Inventors: Jung Hwan Lee, Jung Mi Ko, Ji Hwan Kim, Kwang Ho Baek, Young Don Jung
  • Patent number: 10990196
    Abstract: An electronic device includes a camera module capturing an image, a sensor module recognizing a signal associated with the electronic device or an external object, a first display and a second display, each of which is configured to output content, a memory, and a processor electrically connected to the camera module, the first display, the second display, and the memory. The processor is configured to determine whether the electronic device enters a first state, to capture a source image by using the camera module, when entering the first state, and to generate a first output image output on the first display or a second output image output on the second display based on the source image.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: April 27, 2021
    Inventors: Jung Woo Shin, Ji Young Lee, Jeong Won Ko, Kuk Hwan Kim, Da Hwun Kim, Dong Kyun Kim, Young Mi Kim, Young Seong Kim, Myoung Soo Park, Jung Sik Park, Jung Hee Yeo, Haemi Yoon, Kyung Jun Lee, Hyun Yeul Lee
  • Patent number: 10971234
    Abstract: Provided herein are a page buffer, a memory device having the page buffer, and a method of operating the memory device. The memory device includes a voltage generator configured to generate operating voltages for operating a plurality of memory cells, a program and verify circuit configured to apply the operating voltages to word lines and bit lines coupled to the memory cells and to perform a program operation and a verify operation, and a program operation controller configured to control the program and verify circuit and the voltage generator so that a bit line precharge operation is performed and so that, when the bit line precharge operation has been completed, a bit line discharge operation is performed.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: April 6, 2021
    Assignee: SK hynix Inc.
    Inventors: Jung Hwan Lee, Jung Mi Ko, Ji Hwan Kim, Kwang Ho Baek, Young Don Jung
  • Patent number: 10937513
    Abstract: A semiconductor memory device operates by applying a program pulse to a selected word line, updating a program pulse count value, determining a current sensing mode based upon the program pulse count value, and performing a program verify operation based upon the current sensing mode. The current sensing mode is determined by determining one of an individual state current sensing operation for determining verify pass or fail for one target program state and an all-state current sensing operation for determining verify pass or fail for all target program states.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: March 2, 2021
    Assignee: SK hynix Inc.
    Inventors: Jung Mi Ko, Kwang Ho Baek, Ji Hwan Kim, Seong Je Park, Sung Hoon Ahn, Young Don Jung
  • Publication number: 20200381055
    Abstract: Provided herein may be a semiconductor memory device including a memory cell, a read and write circuit, a current sensing circuit, and control logic. The memory cell array includes a plurality of memory cells. The read and write circuit includes a plurality of page buffers coupled to the plurality of memory cells through a plurality of bit lines, respectively. The current sensing circuit is coupled to the read and write circuit through a plurality of sensing lines. The control logic is configured to control operations of the current sensing circuit and the read and write circuit. At least two page buffers among the plurality of page buffers are coupled to one of the plurality of sensing lines. The control logic controls the read and write circuit to simultaneously perform a current sensing operation for the at least two page buffers.
    Type: Application
    Filed: December 27, 2019
    Publication date: December 3, 2020
    Inventors: Jung Mi KO, Kwang Ho BAEK, Seong Je PARK, Young Don JUNG, Ji Hwan KIM, Jung Hwan LEE
  • Publication number: 20200321042
    Abstract: A memory device includes: a memory block, coupled to a plurality of word lines; a peripheral circuit for performing a sensing operation on selected memory cells of the memory block, the select memory cells being coupled to a selected word line of the plurality of word lines; a word line voltage controller for controlling a sensing voltage applied to the selected word line to perform the sensing operation on the selected memory cells and configured to control a pass voltage applied to the selected word line and unselected word lines of the plurality of word lines, coupled to the memory block; and a bit line control signal generator for controlling the peripheral circuit to apply a channel precharge voltage to respective bit lines, coupled to the selected memory cells, while the pass voltage is being applied to the selected word line and the unselected word lines.
    Type: Application
    Filed: November 6, 2019
    Publication date: October 8, 2020
    Applicant: SK hynix Inc.
    Inventors: Jung Hwan LEE, Jung Mi KO, Ji Hwan KIM, Kwang Ho BAEK, Young Don JUNG
  • Publication number: 20200321058
    Abstract: Provided herein are a page buffer, a memory device having the page buffer, and a method of operating the memory device. The memory device includes a voltage generator configured to generate operating voltages for operating a plurality of memory cells, a program and verify circuit configured to apply the operating voltages to word lines and bit lines coupled to the memory cells and to perform a program operation and a verify operation, and a program operation controller configured to control the program and verify circuit and the voltage generator so that a bit line precharge operation is performed and so that, when the bit line precharge operation has been completed, a bit line discharge operation is performed.
    Type: Application
    Filed: October 31, 2019
    Publication date: October 8, 2020
    Applicant: SK hynix Inc.
    Inventors: Jung Hwan LEE, Jung Mi KO, Ji Hwan KIM, Kwang Ho BAEK, Young Don JUNG
  • Publication number: 20200202963
    Abstract: A semiconductor memory device operates by applying a program pulse to a selected word line, updating a program pulse count value, determining a current sensing mode based upon the program pulse count value, and performing a program verify operation based upon the current sensing mode. The current sensing mode is determined by determining one of an individual state current sensing operation for determining verify pass or fail for one target program state and an all-state current sensing operation for determining verify pass or fail for all target program states.
    Type: Application
    Filed: October 29, 2019
    Publication date: June 25, 2020
    Applicant: SK hynix Inc.
    Inventors: Jung Mi KO, Kwang Ho BAEK, Ji Hwan KIM, Seong Je PARK, Sung Hoon AHN, Young Don JUNG
  • Publication number: 20200135282
    Abstract: A memory device includes a memory cell array including a plurality of memory cells, a plurality of first even page buffers suitable for reading data from first even-numbered memory cells among the plurality of memory cells, and storing the read data, a plurality of first odd page buffers suitable for reading data from first odd-numbered memory cells among the plurality of memory cells, and storing the read data, and a plurality of first cache buffers corresponding to the first even page buffers, suitable for storing data received through a first common node from the first even page buffers, and a plurality of second cache buffers corresponding to the first odd page buffers, and suitable for storing data received through the first common node from the first odd page buffers.
    Type: Application
    Filed: October 24, 2019
    Publication date: April 30, 2020
    Inventors: Jung-Mi KO, Ji-Hwan KIM, Seong-Je PARK